LTC1149 查看數據表（PDF） - Linear Technology

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LTC1149

High Efficiency Synchronous Step-Down Switching Regulators

Linear Technology 

LTC1149

LTC1149-3.3/LTC1149-5

U

OPERATIO (Refer to Functional Diagram)

current is made proportional to the output voltage (mea-

sured by Pin 8) to model the inductor current, which

decays at a rate which is also proportional to the output

voltage. While the timing capacitor is discharging, the

NGATE output is high, turning on the N-channel MOSFET.

When the voltage on the timing capacitor has discharged

past VTH1, comparator T trips, setting the flip-flop. This

causes the NGATE output to go low (turning off the

N-channel MOSFET) and the PGATE output to also go low

(turning the P-channel MOSFET back on). The cycle then

repeats.

As the load current increases, the output voltage

decreases slightly. This causes the output of the gain

stage to increase the current comparator threshold, thus

tracking the load current.

The sequence of events for Burst Mode operation is very

similar to continuous operation with the cycle interrupted

by the voltage comparator. When the output voltage is at

or above the desired regulated value, the P-channel MOSFET

is held off by comparator V and the timing capacitor

continues to discharge below VTH1. When the timing

capacitor discharges past VTH2, voltage comparator S

trips, causing the internal SLEEP line to go low and the

N-channel MOSFET to turn off.

The circuit now enters sleep mode with both power

MOSFETs turned off. In sleep mode, much of the circuitry

is turned off, dropping the supply current from several

milliamperes (with the MOSFETs switching) to 600µA.

When the output capacitor has discharged by the amount

of hysteresis in comparator V, the P-channel MOSFET is

again turned on and this process repeats. To avoid the

operation of the current loop interfering with Burst Mode

operation, a built-in offset is incorporated in the gain

stage. This prevents the current comparator threshold

from increasing until the output voltage has dropped

below a minimum threshold.

To prevent both the external MOSFETs from ever being

turned on at the same time, feedback is incorporated to

sense the state of the driver output pins. Before the N-gate

output can go high, the P-drive output must also be high.

Likewise, the P-drive output is prevented from going low

when the N-gate output is high.

Using constant off-time architecture, the operating fre-

quency is a function of the input voltage. To minimize the

frequency variation as dropout is approached, the off-

time controller increases the discharge current as VIN

drops below VOUT + 1.5V. In dropout the P-channel

MOSFET is turned on continuously.

UU

W

FU CTIO AL DIAGRA Pin 10 connection shown for LTC1149-3.3 and LTC1149-5; changes create LTC1149.

VIN

2

SHDN2

15

LOW

DROPOUT

10V

REGULATOR

CAP

16

VCC

500k

3

14 RGND

5 VCC 500k

1 PGATE

4 PDRIVE

12 PGND

13 NGATE

9 SENSE+

8 SENSE–

SLEEP

S

VTH2

6

CT

R

Q

S

VTH1

–

T

+

OFF-TIME

CONTROL

VIN

SENSE –

V

C

25mV TO 150mV

13k

G

1.25V

7

11 REFERENCE

ITH

SGND

VOS

100k

10

SHDN1

(VFB)

1149 FD

6

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