MC12439FN 查看數據表（PDF） - Motorola => Freescale

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MC12439FN

High Frequency Clock Generator

Motorola => Freescale 

MC12439

SCLOCK

FREF

MCNT

PLL 12439

M COUNTER

VCO_CLK

0

1

SEL_CLK

Shift Reg Out

SDATA SHIFT

REG

12–BIT T0

T1

T2

LATCH

SLOAD

Reset

PLOADB

DECODE

N DIVIDE

(1, 2, 4, 8)

FOUT

(VIA ENABLE GATE)

FDIV4

MCNT

LOW

FOUT

MCNT

FREF

HIGH

7

TEST

MUX

0

TEST

• T2=T1=1, T0=0: Test Mode

• SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin

PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.

Figure 4. Serial Test Clock Block Diagram

DC CHARACTERISTICS (TA = 0 to 70°C; VCC = 3.3 to 5.0V ±5%)

Symbol

Characteristic

Min

Typ

Max

VIH

Input HIGH Voltage

2.0

VIL

Input LOW Voltage

0.8

IIN

Input Current

1.0

IOH

Output HIGH Current (Note 1.)

(FOUT/FOUT Only)

50

VOH

Output HIGH Voltage

TEST

2.5

VOL

Output LOW Voltage

TEST

0.4

VOH

Output HIGH Voltage

FOUT

FOUT

2.27

2.47

VOL

Output LOW Voltage

FOUT

FOUT

1.49

1.68

ICC

Power Supply Current

VCC

PLL_VCC

90

110

15

20

1. Maximum IOH spec implies the device can drive 25Ω impedance with the PECL outputs.

2. See Applications Information section for output level versus frequency information.

3. Output levels will vary 1:1 with VCC variation.

4. 50Ω to VCC – 2.0V pulldown.

Unit

Condition

V

VCC = 3.3 to 5.0V

V

VCC = 3.3 to 5.0V

mA

mA Continuous Current

V

IOH = –0.8mA, (Note 2.)

V

IOL = 0.8mA, (Note 2.)

V

VCC = 3.3V (Notes 3., 4.)

V

VCC = 3.3V (Notes 3., 4.)

mA

TIMING SOLUTIONS

5

BR1333 — Rev 6

MOTOROLA

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