A65H73361 查看數據表（PDF） - AMIC Technology

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A65H73361

128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output

AMIC Technology 

A65H73361/A65H83181 Series

Preliminary

128K x 36 & 256K x 18 Late Write Synchronous

Fast SRAM with Pipelined Data Output

Features

n Fast access times: 2.5/3.0/3.5ns

n 128k x 36 or 256k x 18 organizations

n CMOS technology

n Register to register synchronous operation with self-

timed late write

n Single +3.3V ±5% power supply

n Individual byte write and global write

General Description

The A65H73361 and A65H83181 are 128k words by 36

bits and 256k words by 18 bits late write synchronous

4Mb SRAMS built using high performance CMOS

process.

The differential clock are used to control the timing of

read/write operation and all internal operations are self-

timed. The positive edge triggered CK clock input

controls all addresses write-enables and Synchronous

select and data ins are registered.

n HSTL input & output levels

n Boundary scan(JTAG) IEEE 1149.1 compatible

n Asynchronous output enable

n Sleep mode (ZZ)

n Programmable impedance output drivers

n JEDEC Standard pinout and boundary scan order

n 7 x 17 bump plastic ball grid array (PBGA) package

The data outs are controlled by the output registers off

the next positive clock edge to be updated.

The internal write buffer enables write data to be

accepted on the rising edge of the clock one cycle after

address and control signals.

The SRAM uses HSTL I/O interfaces with programmable

impedance output drivers allowing the outputs to match

the impedance of the circuit traces which reduces signal

reflections.

PRELIMINARY (February, 1999, Version 2.0)

1

AMIC Technology, Inc.

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