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AD5320 查看數據表(PDF) - Analog Devices

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AD5320 Datasheet PDF : 12 Pages
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AD5320
SOT-23 Pin Numbers
Pin
No.
Mnemonic
1
VOUT
2
GND
3
VDD
4
DIN
5
SCLK
6
SYNC
PIN CONFIGURATIONS
SOT-23
SOIC
VOUT 1
GND 2
AD5320
TOP VIEW
6 SYNC
5 SCLK
VDD 3 (Not to Scale) 4 DIN
VDD 1
8 GND
NC 2 AD5320 7 DIN
NC
3
TOP VIEW
(Not to Scale) 6
SCLK
VOUT 4
5 SYNC
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Function
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Ground reference point for all circuitry on the part.
Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and VDD should be de-
coupled to GND.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
Level triggered control input (active low). This is the frame synchronization signal for the input
data. When SYNC goes low, it enables the input shift register and data is transferred in on the
falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless
SYNC is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the DAC.
–4–
REV. B

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