M80C286 查看數據表（PDF） - Intel

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M80C286

HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION

Intel 

M80C286

Table 2 Instruction Set (Continued)

CONDITIONAL TRANSFERS

JA JNBE

Jump if above not below nor equal

JAE JNB

Jump if above or equal not below

JB JNAE

Jump if below not above nor equal

JBE JNA

Jump if below or equal not above

JC

Jump if carry

JE JZ

Jump if equal zero

JG JNLE

Jump if greater not less nor equal

JGE JNL

Jump if greater or equal not less

JL JNGE

Jump if less not greater nor equal

JLE JNG

Jump if less or equal not greater

JNC

Jump if not carry

JNE JNZ

Jump if not equal not zero

JNO

Jump if not overflow

JNP JPO

Jump if not parity parity odd

JNS

Jump if not sign

JO

Jump if overflow

JP JPE

Jump if parity parity even

JS

Jump if sign

UNCONDITIONAL TRANSFERS

CALL

Call procedure

RET

Return from procedure

JMP

Jump

ITERATION CONTROLS

LOOP

Loop

LOOPE LOOPZ

Loop if equal zero

LOOPNE LOOPNZ Loop if not equal not zero

JCXZ

Jump if register CX e 0

INTERRUPTS

INT

Interrupt

INTO

Interrupt if overflow

IRET

Interrupt return

FLAG OPERATIONS

STC

Set carry flag

CLC

Clear carry flag

CMC

Complement carry flag

STD

Set direction flag

CLD

Clear direction flag

STI

Set interrupt enable flag

CLI

Clear interrupt enable flag

EXTERNAL SYNCHRONIZATION

HLT

Halt until interrupt or reset

WAIT

Wait for BUSY not active

ESC

Escape to extension processor

LOCK

Lock bus during next instruction

NO OPERATION

NOP

No operation

EXECUTION ENVIRONMENT CONTROL

LMSW

Load machine status word

SMSW

Store machine status word

Process Control Instructions

ENTER

LEAVE

BOUND

Format stack for procedure entry

Restore stack for procedure exit

Detects values outside

prescribed range

High Level Instructions

Program Transfer Instructions

Memory Organization

Memory is organized as sets of variable length seg-

ments Each segment is a linear contiguous se-

quence of up to 64K (216) 8-bit bytes Memory is

addressed using a two component address (a point-

er) that consists of a 16-bit segment selector and a

16-bit offset see Figure 4 The segment selector in-

dicates the desired segment in memory The offset

component indicates the desired byte address within

the segment

271103 – 3

Figure 4 Two Component Address

5

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