SA624D 查看數據表（PDF） - Philips Electronics

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SA624D

High performance low power FM IF system with high-speed RSSI

Philips Electronics 

Philips Semiconductors

High performance low power FM IF system with

high-speed RSSI

Product specification

SA624

+6V

6.8µF

0.5

to

1.3µH

5.5µH

100nF

10nF

1nF 22pF

NE624 TEST CIRCUIT

5.6pF

44.545

3rd OVERTURE

XTAL

SFG455A3

8

7

6

5

16

0.1µF

SFG455A3

15 14 13 12

0.1µF

0.1µF

11 10

SA602A

0.1µF

SA624

10pF

9

455kHz

Q=20

0.1µF

1

2

3

4

1

2

3

4

5

6

7

8

47pF

22pF

0.21

to

0.28µH

100nF

–0

–20

–40

–60

–80

0.1µF

+6V

VCC

100k

MUTE

RSSI

NE624 IF INPUT (µV) (1500Ω)

10

100

1k

10k

100k

AUDIO

4V

RSSI (VOLTS)

3V

THD + NOISE

2V

AM (80% MOD)

1V

NOISE

DATA

OUT

C–MSG

FILTER

AUDIO

OUT

–120 –100

–80

–60

–40

–20

NE602 RF INPUT (dBm) (50Ω)

Figure 5. Typical Application Cellular Radio (45MHz to 455kHz)

SR00444

CIRCUIT DESCRIPTION

The SA624 is a very high gain, high frequency device. Correct

operation is not possible if good RF layout and gain stage practices

are not used. The SA624 cannot be evaluated independent of

circuit, components, and board layout. A physical layout which

correlates to the electrical limits is shown in Figure 3. This

configuration can be used as the basis for production layout.

The SA624 is an IF signal processing system suitable for IF

frequencies as high as 21.4MHz. The device consists of two limiting

amplifiers, quadrature detector, direct audio output, muted audio

output, and signal strength indicator (with output characteristic). The

sub-systems are shown in Figure 4. A typical application with

45MHz input and 455kHz IF is shown in Figure 5.

IF Amplifiers

The IF amplifier section consists of two log-limiting stages. The first

consists of two differential amplifiers with 39dB of gain and a small

signal bandwidth of 41MHz (when driven from a 50Ω source). The

output of the first limiter is a low impedance emitter follower with

1kΩ of equivalent series resistance. The second limiting stage

consists of three differential amplifiers with a gain of 62dB and a

small signal AC bandwidth of 28MHz. The outputs of the final

differential stage are buffered to the internal quadrature detector.

One of the outputs is available at Pin 9 to drive an external

quadrature capacitor and L/C quadrature tank.

Both of the limiting amplifier stages are DC biased using feedback.

The buffered output of the final differential amplifier is fed back to the

input through 42kΩ resistors. As shown in Figure 4, the input

impedance is established for each stage by tapping one of the

feedback resistors 1.6kΩ from the input. This requires one

additional decoupling capacitor from the tap point to ground.

42k

V+

15

16

70014

1.6k

7k

1

40k

SR00445

Figure 6. First Limiter Bias

Because of the very high gain, bandwidth and input impedance of

the limiters, there is a very real potential for instability at IF

frequencies above 455kHz. The basic phenomenon is shown in

Figure 8. Distributed feedback (capacitance, inductance and

radiated fields)

1997 Nov 07

7

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