V380SDC 查看數據表（PDF） - QuickLogic Corporation

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V380SDC

High Performance SDRAM Controller for 32-bit and 64-bit Embedded Processors

QuickLogic Corporation 

Pin Description

Table 3: Signal Descriptions (cont’d)

Signal

SCL

CLK

RSTIN

VCC

GND

Type

OD

I

I

—

—

Ra

Description

Z Serial EEPROM Clock

Clock and Reset

Clock Input

Reset Input Active low reset input used to initialize all internal

functions of the chip.

Power and Ground Signals

POWER leads for external connection to a 3.3 V VCC board plane.

GROUND leads for external connection to a GND board plane.

a. R indicates state during reset.

© 2000 V3 Semiconductor Corp.

V380SDC_A0 Datasheet Rev 1.01 DS-SD01-0101

5

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