P4C1256 查看數據表（PDF） - Performance Semiconductor

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P4C1256

HIGH SPEED 32K x 8 STATIC CMOS RAM

Performance Semiconductor 

P4C1256

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(6)

ADDRESS

CE

tWC (9)

tAS

tCW

tAW

tAH

WE

DATA IN

DATA OUT(6)

tWP

tDW

tDH

DATA VALID

HIGH IMPEDANCE

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

TRUTH TABLE

Mode

CE1 CE2 OE

Standby H X X

Standby X L X

DOUT

Disabled L

HH

Read

L HL

Write

L HX

WE I/O Power

X High Z Standby

X High Z Standby

H High Z Active

H DOUT Active

L High Z Active

DOUT

255Ω

+5V

480Ω

30pF* (5pF* for t HZ , t LZ , t OHZ ,

tOLZ, tWZ and tOW )

D OUT

R TH = 166.5 Ω

VTH = 1.73 V

30pF* (5pF* for t HZ , t LZ , t OHZ,

t OLZ, t WZ and tOW )

Figure 1. Output Load

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P4C1256, care must be taken

when testing this device; an inadequate setup can cause a normal

functioning part to be rejected as faulty. Long high-inductance leads that

cause supply bounce must be avoided by bringing the VCC and ground

planes directly up to the contactor fingers. A 0.01 µF high frequency

capacitor is also required between V and ground. To avoid signal

CC

Figure 2. Thevenin Equivalent

reflections, proper termination must be used; for example, a 50Ω test

environment should be terminated into a 50Ω load with 1.73V (Thevenin

Voltage) at the comparator input, and a 116Ω resistor must be used in

series with DOUT to match 166Ω (Thevenin Resistance).

122

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