MCM69L817ZP7 查看數據表（PDF） - Signal Processing Technologies

零件编号

产品描述 (功能)

生产厂家

MCM69L817ZP7

S2ADC™ - Simultaneous Sampling Analog to Digital Converter

Signal Processing Technologies 

Layout Considerations (cont.)

supply lines can degrade the converters

performance, especially corrupting are noise

and spikes from a switching power supply.

The ground pins (AGND and VSS) on the

SP8530 are separated internally and should be

connected to each other under the converter.

Applying the technique of using separate

analog and digital ground planes is usually the

best way to preserve dynamic performance and

reduce noise coupling into sensitive converter

circuits. Where any compromise must be made

the common return of the analog input signal

should be referenced to the AGND pin of the

converter. This prevents any voltage drops that

might occur in the power supply's common

return from appearing in series with the input

signal.

Coupling between analog and digital lines should

be minimized by careful layout. For instance, if

analog and digital lines must cross they should

do so at right angles. Parallel analog and digital

lines should be separated from each other by a

trace connected to common.

If external gain and offset potentiometers are

used, the potentiometers and related resistors

should be located as close to the SP8530 as

possible.

Minimizing “Glitches”

Coupling of external transients into an analog to

digital converter can cause errors which are

difficult to debug. In addition to the above

discussions on layout considerations, bypassing

and grounding, there are several other useful

steps that can be taken to get the best analog

performance from a system using the SP8530

converters. These potential system problem

sources are particularly important to consider

when developing a new system, and looking for

causes of errors in breadboards.

First, care should be taken to avoid transients

during critical times in the sampling and

conversion process. Since the SP8530 has a

internal sample/hold function, the signal that

puts the device into hold state (CS going low) is

critical, as it would be on any sample/hold

amplifier. The CS falling edge should have a 5

to 10 ns transition time, low jitter, and have

minimal ringing, especially during the first 20ns

after it falls.

SP8530DS/01

SP8530 S2ADCTM - Simultaneous Sampling Analog to Digital Converter

7

© Copyright 2000 Sipex Corporation

Share Link: