NT256D64S8HA0G 查看數據表（PDF） - Unspecified

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NT256D64S8HA0G

256MB : 32M x 64 PC2100 / PC1600 Unbuffered DIMM

Unspecified 

NT256D64S8HA0G

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DIMM

Operating, Standby, and Refresh Currents

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

PC1600

Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;

I DD0

tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

1000

Operating Current : one bank; active / read / precharge; Burst = 2;

I DD1

tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;

address and control inputs changing once per clock cycle

1120

Precharge Power-Down Standby Current :

I DD2P

all banks idle; power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)

240

Idle Standby Current : CS ≥ VIH (MIN) ; all banks idle; CKE >= VIH(MIN) ;

I DD2N

tCK = tCK (MIN) ; address and control inputs changing once per clock cycle

480

Active Power-Down Standby Current : one bank active;

I DD3P

power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)

240

Active Standby Current : one bank; active / precharge; CS ≥ VIH (MIN) ;

CKE ≥ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS

I DD3N inputs changing twice per clock cycle;

800

address and control inputs changing once per clock cycle

Operating Current : one bank; Burst = 2; reads; continuous burst;

I DD4R

address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5;

1640

tCK = tCK (MIN) ; IOUT = 0mA

Operating Current : one bank; Burst = 2; writes; continuous burst;

I DD4W

address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5;

1320

tCK = tCK (MIN)

I DD5 Auto-Refresh Current :

t RC = t RFC (MIN)

t RC = 15.625 µs

1840

252

I DD6 Self-Refresh Current : CKE ≤ ?0.2V

32

1. I DD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns .

3. Enables on-chip refresh and address counters.

4. Current at 15.625 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 15.625 µs.

PC2100

1160

Unit Notes

mA

1,2

1360

240

560

240

mA

1,2

mA

1,2

mA

1,2

mA

1,2

960

mA

1,2

1800

mA

1,2

1680

2400

252

32

mA

1,2

mA

1,2

mA

1,2,4

mA

1,2,3

Preliminary

8

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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