V436516R04VATG-10PC 查看數據表（PDF） - Mosel Vitelic, Corp

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V436516R04VATG-10PC

3.3 VOLT 16M x 64 (using 8M x 16) PC100 UNBUFFERED SDRAM MODULE

Mosel Vitelic, Corp 

MOSEL VITELIC

SPD-Table for PC100 modules: (Continued)

Byte Number Function Described

31

Module Bank Density (Per Bank)

32

SDRAM Input Setup Time

33

SDRAM Input Hold Time

34

SDRAM Data Input Setup Time

35

SDRAM Data Input Hold Time

62-61

Superset Information (May be used in Future)

62

SPD Revision

63

Checksum for Bytes 0 - 62

64

Manufacturer’s JEDEC ID Code

65-71

Manufacturer’s JEDEC ID Code (cont.)

72

Manufacturing Location

73-90

Module Part Number (ASCII)

91-92

PCB Identification Code

93

Assembly Manufacturing Date (Year)

94

Assembly Manufacturing Date (Week)

95-98

Assembly Serial Number

99-125

Reserved

126

Intel Specification for Frequency

127

Reserved

128+

Unused Storage Location

DC Characteristics

TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V

Symbol Parameter

VIH

Input High Voltage

VIL

Input Low Voltage

VOH

Output High Voltage (IOUT = –2.0 mA)

VOL

Output Low Voltage (IOUT = 2.0 mA)

II(L)

Input Leakage Current, any input

(0 V < VIN < 3.6 V, all other inputs = 0V)

IO(L)

Output leakage current

(DQ is disabled, 0V < VOUT < VCC)

V436516R04VATG-10PC

SPD Entry Value

128 MByte

2.0 ns

1.0 ns

2.0 ns

1.0 ns

Revision 1.2

Mosel Vitelic

V436516R04VATG-10PC

Hex Value

16Mx64

20

20

10

20

10

00

12

95

40

00

00

100 MHz

64

00

00

Limit Values

Min.

Max.

2.0

–0.5

V CC +0.3

0.8

2.4

—

—

0.4

–40

40

–40

40

Unit

V

V

V

V

µA

µA

V436516R04VATG-10PC Rev. 1.1 February 2001

5

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