V436516R04VATG-10PC 查看數據表（PDF） - Mosel Vitelic, Corp

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V436516R04VATG-10PC

3.3 VOLT 16M x 64 (using 8M x 16) PC100 UNBUFFERED SDRAM MODULE

Mosel Vitelic, Corp 

MOSEL VITELIC

V436516R04VATG-10PC

AC Characteristics 3,4

TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns (Continued)

Limit Values

# Symbol

Refresh Cycle

17

tSREX

18

tREF

Read Cycle

19

tOH

20

tLZ

21

tHZ

22

tDQZ

Write Cycle

23

tDPL

24

tDAL

25

tDQW

Parameter

Self Refresh Exit Time

Refresh Period (4096 cycles)

Data Out Hold Time

Data Out to Low Impedance Time

Data Out to High Impedance Time

DQM Data Out Disable Latency

Data input to Precharge (write recovery)

Data In to Active/refresh

DQM Write Mask Latency

-10PC

Min.

Max.

Unit

Note

10

–

ns

9

64

–

ms

8

3

–

ns

4

0

–

ns

3

9

ns

10

2

–

CLK

2

–

CLK

5

–

CLK

11

0

–

CLK

Notes:

1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No

Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module

bank.

2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).

3. All AC characteristics are shown for device level.

An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed

by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.

4. AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition

time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit

shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with

a input signal of 1V / ns edge rate between 0.8V and 2.0V

V436516R04VATG-10PC Rev. 1.1 February 2001

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