LTC694CN8-3.3-TRPBF 查看數據表（PDF） - Linear Technology

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LTC694CN8-3.3-TRPBF

3.3V Microprocessor Supervisory Circuits

Linear Technology 

LTC694-3.3/LTC695-3.3

APPLICATIONS INFORMATION

If battery connections are made through long wires, a

10Ω to 100Ω series resistor and a 0.1μF capacitor are

recommended to prevent any overshoot beyond VCC due

to the lead inductance (Figure 4).

Table 1 shows the state of each pin during battery back-up.

When the battery switchover section is not used, connect

VBATT to GND and VOUT to VCC.

Table 1. Input and Output Status in Battery Back-Up Mode

SIGNAL STATUS

VCC

VOUT

VBATT

BATT ON

PFI

PFO

C2 monitors VCC for active switchover.

VOUT is connected to VBATT through an internal PMOS switch.

The supply current is 1μA maximum.

Logic high. The open-circuit output voltage is equal to VOUT.

Power failure input is ignored.

Logic low.

RESET Logic low.

RESE_T Logic high. The open-circuit output voltage is equal to VOUT.

LOW LINE Logic low.

WDI

WDO

CE IN

CE OUT

OSC IN

Watchdog input is ignored.

Logic_ high. The open-circuit output voltage is equal to VOUT.

Chip Enable input is ignored.

Logic high. The open-circuit output voltage is equal to VOUT.

OSC IN is ignored.

OSC SEL OSC SEL is ignored.

10Ω

2.7M

VBATT

0.1μF

LTC694-3.3

LTC695-3.3

GND

694/5-3.3 F04

Figure 4. 10Ω/0.1μF Combination Eliminates Inductive

Overshoot and Prevents Spurious Resets During Battery

Replacement. The 2.7M Pulls the VBATT Pin to Ground

While the Battery is Removed, Eliminating Spurious Resets

Memory Protection

The LTC695-3.3 includes memory protection circuitry

which ensures the integrity of the data in memory by pre-

venting write operations when VCC is at invalid lev_el. Two

additional pins, CE IN and CE OUT, control the Chip Enable

or Write inputs of CMOS RAM. When VCC is 3.3V, CE OUT

follows CE IN with a typical propagation delay of 30ns.

When VCC falls below the reset voltage threshold or VBATT,

CE OUT is forced high, independent of CE IN. CE OUT is

an alternative signal to drive the CE, CS, or Write input of

battery backed up CMOS RAM. CE OUT can also be used

to drive the Store or Write input of an EEPROM, EAROM

or NOVRAM to achieve similar protection. Figure 5 shows

the timing diagram of CE IN and CE OUT.

VCC

CE IN

V2

V1

V1 = RESET VOLTAGE THRESHOLD

V2 = RESET VOLTAGE THRESHOLD +

RESET THRESHOLD HYSTERESIS

CE OUT

VOUT = VBATT

Figure 5. Timing Diagram for CE IN and CE OUT

VOUT = VBATT

694/5-3.3 F05

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