70FL256P0XBHI20 查看數據表（PDF） - Cypress Semiconductor
零件编号
产品描述 (功能)
生产厂家
70FL256P0XBHI20 Datasheet PDF : 16 Pages
| |||
S70FL256P
4. Only applicable as a constraint for WRR instruction when SRWD is set to a ‘1’.
5. tWH + tWL must be less than or equal to 1/fC.
6. Full Vcc range (2.7 – 3.6V) and CL = 30 pF.
7. Regulated Vcc range (3.0 – 3.6V) and CL = 30 pF.
8. Bulk Erase is on a die per die basis, not for the whole device.
9. When switching between die, a minimum time of tCS must be kept between the rising edge of one chip select and the falling edge of the other for operations and data
to be valid.
9.1 Capacitance
Symbol
Parameter
Test Conditions Min Typ
CIN
COUT
Notes:
Input Capacitance
(applies to CS1#, CS2#, SCK, SI/IO0, SO/IO1, W#/ACC/IO2,
HOLD#/IO3)
Output Capacitance
(applies to SI/IO0, SO/IO1, W#/ACC/IO2, HOLD#/IO3)
n VOUT = 0V
Desig VIN = 0V
10.0
22.0
1. Sampled, not 100% tested.
w 2. Test conditions TA = 25°C, f = 1.0 MHz.
Not Recommended for Ne 3. For more information on pin capacitance, please consult the IBIS models.
Max Unit
16.0 pF
30.0 pF
Document Number: 002-00647 Rev. *F
Page 10 of 16
Share Link: 