29C010JI-3 查看數據表（PDF） - Turbo IC Inc

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29C010JI-3

HIGH SPEED CMOS 1 Megabit PROGRAMMABLE and ERASABLE ROM 128K X 8 BIT FLASH PEROM

Turbo IC Inc 

Turbo IC, Inc.

29C010

ADVANCE INFORMATION

PIN DESCRIPTION

ADDRESSES (A0 - A16)

The Addresses are used to select an 8 bits memory location during a

program or read operation.

CHIP ENABLE (CE)

The Chip Enable input must be low to enable all read/program operations

on the device. By setting CE high, the device is disabled and the power

consumption is extremely low with the standby current below 100 µA.

OUTPUT ENABLE (OE)

The Output Enable input activates the output buffers during the read op-

erations.

WRITE ENABLE (WE)

The Write Enable input initiates the programming of data into the memory.

DATA INPUT/OUTPUT (I/O0-I/O7)

Data Input/Output pins are used to read data out of the memory or to

program Data into the memory.

DEVICE OPERATION

READ

TOGGLE BIT

The 29C010 is accessed like a static RAM. Read operations are initiated

by both CE and OE on low and terminated by either CE or OE returning

high. The outputs are at the high impedance state whenever CE or OE

returns high. The two line control architecture gives designers flexibility in

preventing bus contention.

PROGRAM

A program cycle is initiated when CE and WE are low and OE is high. The

address is latched internally on the falling edge of the CE or WE, which-

ever occurs last. The data is latched by the rising edge of CE or WE,

whichever occurs first. Once a programming cycle has been started, the

internal timer automatically generates the program sequence to the comple-

tion of the program operation.

SECTOR PROGRAM OPERATION

In addition to DATA Polling the 29C010 provides another method for deter-

mining the end of a programming or erase cycle. During a program

or erase operation, successive attempts to read data from the device will

result in I/O6 toggling between one and zero. Once the program cycle has

completed, I/O6 will stop toggling and valid data will be read. Examining

the toggle bit may begin at any time during a program cycle.

CHIP CLEAR

The content of the entire memory array of the 29C010 may be altered to

HIGH by the use of the CHIP CLEAR operation. By setting CE to low, OE

to 12 Volts, and WE to low, the entire memory array can be cleared (written

HIGH) within 20 ms. The CHIP CLEAR operation is a latch operation mode.

After CE, WE, and OE get the CHIP CLEAR process started, the internal

chip timer takes over the CHIP CLEAR operation and CE, OE, or WE

becomes free to be used by the system for other purposes.

The device is reprogrammed on a sector basis. When a byte of data within

a sector is to be changed, data for the entire sector must be loaded into the

device. Any byte that is not loaded during the programming of its sector will

be erased to read FFh. The programming operation of the 29C010 allows

128 bytes of data to be serially loaded into the device and then simulta-

neously written into memory during the internally generated program cycle.

After the first byte has been loaded, successive bytes of data must be

loaded until the full sector of 128 bytes is loaded. Each new byte to be

written must be loaded within 300 µs of the previously loaded byte. The

sector address defined by the addresses A7 - A16 is latched by the first

CE or WE falling edge which initiates a program cycle and they stay latched

until the completion of the program cycle. Any changes in the sector ad-

dresses during the load-program cycle will not affect the initially latched

sector address. Addresses A0 - A6 are used to define which bytes will be

loaded within the 128 bytes sector. The bytes may be loaded in any order

that is convenient to the user. The content of a loaded byte may be altered

at any time during the loading cycle if the maximum allowed byte-load time

(300 µs) is not exceeded. All the 128 bytes of the page are serially loaded

and are programmed in a single 10 ms program cycle

DATA POLLING

The 29C010 features DATA Polling to indicate the completion of a program

cycle to the host system. During a program cycle, an attempted read of the

last byte loaded into the page will result in the complement of the loaded

byte on I/O7, i.e., loaded 0 would be read 1. Once the program cycle has

been completed, true data is valid on all outputs and the next cycle may

be started. DATA Polling may begin at any time during the programming

cycle.

HARDWARE DATA PROTECTION

The 29C010 has three hardware features to protect the written content of

the memory against inadvertent programming:

a) Vcc threshold detector - If Vcc is below 3 V the program capabilities of

the chip is inhibited for whatever input conditions.

b) Noise protection - A WE, OE, or CE pulse of less than 10 ns in width is

not able to initiate a program cycle.

c) Write inhibit - Holding OE at low, or CE at high, or WE at high inhibits the

program cycle.

SOFTWARE DATA PROTECTION

The 29C010 offers a software controlled data program protection feature.

The device is delivered to the user with the software data protection DIS-

ABLED, i.e., the device will go to the program operation as long as Vcc

exceeds 3 V and CE, WE, and OE inputs are set at program mode levels.

The 29C010 can be automatically protected against an accidental write

operation during power-up or power-down without any external circuitry by

enabling the software data protection feature. This feature is enable after

the first program cycle which includes the software algorithm. After this

operation is done the program function of the device may be performed

only if every program cycle is preceded by the software algorithm. The

device will maintain its software protect feature for the rest of its life, unless

the software algorithm for disabling the protection is implemented.

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