ST40RA 查看數據表（PDF） - STMicroelectronics

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ST40RA

32-bit Embedded SuperH Device

STMicroelectronics 

ST40RA

4 Architecture

4.3.2

PCI interface

The PCI interface complies to the PCI v2.1 and Power Management Interface V1.0 specifications. It

is 32 bits wide and operates at 33 or 66 MHz. Master and target mode are supported. A PCI arbiter

and clock generator is provided inside the ST40RA. For details on the configuration options for the

PCI interface please see ST40 System Architecture Manual, Volume 2: Bus Interfaces.

4.3.3

EMI/MPX interface

The EMI/MPX interface contains the following blocks. For full details of the configuration options of

the EMI please see the ST40 System Architecture Manual, Volume 2: Bus Interfaces.

EMI memory interface initiator

The EMI provides access to ROMs, SDRAM, memory mapped asynchronous external peripherals

and synchronous MPX bus peripherals. The EMI supports burst mode flash ROM and MPX for

memory-mapped device coupling. The ST40RA GPDMA unit accesses external devices and two

sets of DMA channels control signals are provided for this purpose.

EMPI memory interface target

The EMPI is a synchronous MPX target that allows for an external MPX initiator to access the

ST40RA internal memory space. The EMPI contains a general purpose control channel and four

high performance channels each of which implements a write buffer and a pair of 32-byte read-

ahead buffers able to optimize external device burst access to and from the ST40RA internal

memory. These buffers can be associated with memory regions within the ST40RA and external

DMA channels. Four sets of DMA handshake signals are provided to the EMPI to optimize long

burst transfers between the ST40RA and external initiators like the STi5514.

MPX bus arbiter

The ST40RA has an internal programmable bus arbiter to optimize utilization of the MPX bus. The

ST40RA MPX arbiter supports one external initiator and has programmable bus priority (ST40RA or

external device), bus parking (ST40RA, external, idle or last user) and latency timers. The internal

arbiter can be bypassed if an external arbiter supporting more initiators is required.

4.4 I/O devices

4.4.1

Mailbox

The ST40 and the external microprocessor communicate with each other and synchronize their

activities using the memory-mapped mailbox. Processes generate interrupts to either CPU, and

send and receive messages between the two CPUs. There are buffers for message queueing in

both directions and interrupt bits can be set in each direction. Access to the mailbox from external

devices is through the ST40RA EMPI or the PCI target interface.

4.5 Software

4.5.1

Development systems and software

The ST40RA supports application development, with a full range of debug features and an

emulation mode (ASE). The ASE mode has a dedicated 1-Kbyte buffer for emulator firmware,

supporting performance counters and branch trace. The ST40RA, with its memory management

unit, supports standard operating systems including WindowsCE and Linux. The ST40 has a wide

range of development support from ST and third parties, and efficiently runs applications written in

C, C++ and Java.

ADCS 7260755H

STMicroelectronics 10/94

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