ST40RA 查看數據表（PDF） - STMicroelectronics

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ST40RA

32-bit Embedded SuperH Device

STMicroelectronics 

ST40RA

4 Architecture

Floating point unit/multiply and accumulate

The on-chip, floating point coprocessor executes single precision (32-bit) and double precision

(64-bit) operations. It has a five-stage pipeline and supports IEEE754-compliant data types and

exceptions. It has rounding modes: (round-to-nearest) and (round-to-zero), and handles

denormalized numbers (truncation-to-zero) or interrupt generation for compliance with IEEE754.

The floating point unit performs the following functions:

q fmac (multiply-and-accumulate), fdiv (divide),

q fsqrt (square root) instructions,

q 3-D graphics instructions (single-precision):

­ 4-dimensional vector conversion and matrix operations (ftrv): 4 cycles (pitch), 7 cycles

(latency),

­ 4-dimensional vector (fipr) inner product: 1 cycle (pitch), 4 cycles (latency).

MMU configuration

There is 4 Gbytes virtual address space with 256 address space identifiers (8-bit ASIDs),

supporting single virtual and multiple virtual memory modes. Page sizes are 1 Kbyte, 4 Kbytes, 64

Kbytes or 1 Mbyte. The MMU supports four-entry, fully associative ITLB for instructions and

64-entry fully associative UTLB for instructions and operands. Software-controlled replacement and

random-counter replacement algorithms are also supported. The physical address space is 512

Mbytes (29-bit), see Figure 2: System address organization on page 12.

Cache

8 Kbytes of direct-mapped instruction cache are organized as 256 32-byte lines, and 16 Kbytes of

direct-mapped operand cache are organized as 512 32-byte lines. RAM mode (8-Kbyte cache plus

8-Kbyte RAM) with selectable write method (copy back or write through) is supported. A single

stage buffer for copy-back and a single stage buffer for write-through are available. The cache

contents can be address mapped and there is a 32-byte two-entry store queue.

4.2.2

SuperHyway internal interconnect

The ST40RA uses the SuperHyway memory mapped packet router for on-chip intermodule

communication. The interconnect supports a split transaction system allowing a nonblocking high

throughput, low latency system to be built. There are separate request and response packet

routers.

The ST40RA SuperHyway implementation is show in Section 5.8: Memory bridge control on

page 21. The interconnect allows simultaneous requests between multiple modules and is able to

ensure a very high data throughput with in many cases zero routing, arbitration and decode

latencies.

4.2.3 Standard ST40 peripherals

Synchronous serial channel

There are two ST40 compatible full duplex communication channels (SCIF1, SCIF2).

Asynchronous mode is supported. A separate 16-byte FIFO is provided for the transmitter and

receiver.

Interrupt controller

The interrupt controller supports all of the on-chip peripheral module interrupts, and five external

interrupts (NMI and IRL0 to IRL3). The priority can be set for each on-chip peripheral module

interrupt. IRL0 to IRL3 are configured as four independent interrupts or encoded to provide 15

external interrupt levels.

ADCS 7260755H

STMicroelectronics

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