ML65245 查看數據表（PDF） - Micro Linear Corporation

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ML65245

High Speed Octal Buffer Transceivers

Micro Linear Corporation 

ML65245**/ML65L245*

APPLICATION 2

BUFFERING CACHE MEMORY

With the advent of higher power operating systems like

Windows NT, NeXT Step, Windows, OS/2 Warp, etc.,

RISC processor designs such as the Mips R4000 series are

gaining momentum. In these systems the interface to

secondary cache has a critical path in the address and bus

control pins. As shown in Figure 8, any propagation delay

time saved in the buffer translates to a slower SRAM

access requirement and is therefore less expensive.

Currently, the secondary cache bus operates at 75MHz.

In order to meet the 13ns cycle time, the SRAM and buffer

must meet a total access time of 12ns. With the ML65245,

the required SRAM access time is 10ns at 75MHz and

18ns at 50MHz. With the fastest FCT buffer available

(3.2ns), the SRAM access time required in the above

scenarios would be 8ns and 15ns respectively. This access

time difference could mean the difference between using

expensive BiCMOS SRAMs versus less expensive CMOS

SRAMs.

R4X00

150/75 MHz

ADDR

OE

CS

ML65245

SRAM

10ns

SRAM

10ns

DATA BUS

SECONDARY CACHE MODULE

Figure 8. ML65245 in a R4X00 secondary cache application. The address and control signal path is critical and

loads the R4X00 output pins. The ML65245 buffer alleviates the load on the R4X00 and because it is fast,

slower, less expensive SRAMs can be used.

ADDR

WE

DATA

ADDR1

tA

tH

Figure 9. Timing waveform showing address buffer switching rate (tA + tH) in a secondary cache module.

8

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