HV430WG 查看數據表（PDF） - Supertex Inc

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HV430WG

High-Voltage Ring Generator

Supertex Inc 

Supertex inc.

HV430

High-Voltage Ring Generator

Features

► 105Vrms ring signal

► Output overcurrent protection

► 5.0V CMOS logic control

► Logic enable/disable to save power

► Adjustable deadband in single-control mode

► Power-on reset

► Fault output for problem detection

Applications

► Line access cards

► Set-top/Street box

The RESET input functions as a power-on reset when

connected to an external capacitor. The FAULT output

indicates an overcurrent condition and is cleared after 4

consecutive cycles with no overcurrent condition. A logic low

on RESET or ENABLE clears the FAULT output. It is active-

low and open-drain to allow wire OR’ing of multiple drivers.

PGATE and NGATE are controlled independently by logic inputs

PIN and NIN when the MODE pin is at logic high. A logic high on

PIN will turn on the external P-channel MOSFET. Similarly, a

logic high on NIN will turn on the external N-channel MOSFET.

Lockout circuitry prevents the N and P switches from turning

on simultaneously. A pulse width limiter restricts pulse widths

to no less than 100 - 200ns.

General Description

The Supertex HV430 is a high voltage PWM ring generator

integrated circuit. The high voltage outputs, VPGATE and

VNGATE, are used to drive the gates of external high voltage

N-channel and P-channel MOSFETs in a push-pull

configuration. Overcurrent protection is implemented for

both the P-channel and N-channel MOSFETs. External

sense resistors set the over-current trip point.

For applications where a single control input is desired, the

MODE pin should be connected to SGND. The PWM control

signal is then input to the NIN pin. A user-adjustable deadband

in the control logic ensures break-before-make on the outputs,

thus avoiding cross conduction on the high voltage output

during switching. A logic high on NIN will turn the external P-

Channel MOSFET on and the N-Channel off, and vice versa.

The IC can be powered down by applying a logic low on the

ENABLE pin, placing both external MOSFETs in the off state.

Functional Block Diagram

VDD

FAULT

De-glitcher

clk reset

PIN

MODE

DEADBAND

NIN

Control

Logic

+5.0V

VDD

VPP2

VPP2

Regulator

VPP1

Down

Translator

Up

Translator

Current

Trip

P

Driver

Up

Translator

N

Driver

VPSEN

VPGATE

VNGATE

VPP1

RSENSE

Ringer

Output

ENABLE

RESET

VDD

10µA

Doc.# DSFP-HV430

A031414

Down

Translator

Current

Trip

SIG PWR

GND GND

VNN2

Regulator

VNN2

VNSEN

VNN1

RSENSE

VNN1

Supertex inc.

www.supertex.com

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