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AD783
(Rev.:RevA)

Complete Very High Speed Sample-and-Hold Amplifier

Analog Devices 

AD783

DYNAMIC PERFORMANCE

The AD783 is compatible with 12-bit A-to-D converters in

terms of both accuracy and speed. The fast acquisition time, fast

hold settling time and good output drive capability allow the

AD783 to be used with high speed, high resolution A-to-D

converters like the AD671 and AD7586. The AD783’s fast

acquisition time provides high throughput rates for multichannel

data acquisition systems. Typically, the AD783 can acquire a

5 V step in less than 250 ns. Figure 1 shows the settling

accuracy as a function of acquisition time.

0.08

0.06

(VOUT HOLD – VIN), mV

+1

V IN , VOLTS

–2.5

+2.5

GAIN ERROR

NONLINEARITY

HOLD MODE OFFSET

–1

0.04

0.02

0

0

250

500

ACQUISITION TIME – ns

Figure 1. VOUT Settling vs. Acquisition Time

The hold settling determines the required time, after the hold

command is given, for the output to settle to its final specified

accuracy. The typical settling behavior of the AD783 is 150 ns.

The settling time of the AD783 is sufficiently fast to allow the

SHA, in most cases, to directly drive an A-to-D converter

without the need for an added “start convert” delay.

HOLD MODE OFFSET

The dc accuracy of the AD783 is determined primarily by the

hold mode offset. The hold mode offset refers to the difference

between the final held output voltage and the input signal at the

time the hold command is given. The hold mode offset arises

from a voltage error introduced onto the hold capacitor by

charge injection of the internal switches. The nominal hold

mode offset is specified for a 0 V input condition. Over the in-

put range of –2.5 V to +2.5 V, the AD783 is also characterized

for an effective gain error and nonlinearity of the held value, as

shown in Figure 2. As indicated by the AD783 specifications,

the hold mode offset is very stable over temperature.

Figure 2. Hold Mode Offset, Gain Error and Nonlinearity

For applications where it is important to obtain zero offset, the

hold mode offset may be nulled externally at the input to the

A-to-D converter. Adjustment of the offset may be accom-

plished through the A-to-D itself or by an external amplifier

with offset nulling capability (e.g., AD711). The offset will

change less than 0.5 mV over the specified temperature range.

SUPPLY DECOUPLING AND GROUNDING

CONSIDERATIONS

As with any high speed, high resolution data acquisition system,

the power supplies should be well regulated and free from

excessive high frequency noise (ripple). The supply connection

to the AD783 should also be capable of delivering transient

currents to the device. To achieve the specified accuracy and

dynamic performance, decoupling capacitors must be placed

directly at both the positive and negative supply pins to com-

mon. Ceramic type 0.1 µF capacitors should be connected from

VCC and VEE to common.

ANALOG

P.S.

+5V

C –5V

DIGITAL

P.S.

C +5V

0.1µF 0.1µF

1µF 1µF

1µF

INPUT

AD783

ANALOG-TO-DIGITAL

CONVERTER

DIGITAL

DATA

OUTPUT

SIGNAL GROUND

Figure 3. Basic Grounding and Decoupling Diagram

–6–

REV. A

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