AD783 查看數據表（PDF） - Analog Devices

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AD783

Complete Very High Speed Sample-and-Hold Amplifier

Analog Devices 

AD783

AD783 TO AD670 INTERFACE

The 15 MHz small signal bandwidth of the AD783 makes it a

good choice for undersampling applications. Figure 8 shows

the interface between the AD783 and the AD670 ADC, where

the AD783 samples the incoming IF signal. For this particular

application, the IF carrier was 10.7 MHz and the information

signal was a 5 kHz FSK-modulated tone. The sample-and-hold

signal is applied to the 8-bit AD670 ADC and then digitally

processed for analysis.

The CLKIN signal is connected directly to the S/H pin of the

AD783 and must comply with the acquisition and settling re-

quirements of the SHA. A delayed version of CLKIN is applied

to the R/W input of the AD670 in order to accommodate the

hold-mode settling requirements of the AD783. The 10 µs con-

version speed of the AD670 combined with the 150 ns hold-

mode settling time of the AD783 result in a total system

throughput of 10.15 µs.

By keeping the 10.7 MHz IF input to the AD783 at a low

amplitude, 255 mV p-p, the resultant distortion and jitter-

induced noise result in approximately 45 dB of dynamic range.

The AD670 can be conveniently configured such that its full-

scale input range is 255 mV in order to retain the full 8-bit

dynamic range of the converter. The maximum sample rate of

the AD670 is 10 µs; therefore, to comply with the Nyquist

criteria the maximum information bandwidth is 50 kHz.

The low going one-shot output is connected to the clock input

of flip-flop2. The D2 input of flip-flop2 is tied high. The rising

edge of the low going pulse toggles the Q2 output of flip-flop2 to

a high state. This output, which is tied to the ENCODE input of

the AD671, initiates a conversion of the buffered output signal

of the AD783. The AD671 issues the signal DAV when the con-

version is complete. The DAV signal is tied to the asynchronous

CLR1 and CLR2 inputs of both flip-flops. When DAV goes low,

the Q1 output goes high returning the AD783 to the sample or

acquisition mode. The Q2 output (ENCODE) returns low until

it is again triggered by the rising edge of the one-shot output.

VIN

AD783

AD84X

AIN

CLOCK

+5V

ONE-

SHOT

Q1

D1 CLR1

D2 CLR2

Q2

AD671

DAV

ENCODE

Figure 9. AD783 to AD671 Interface

10.7MHz

255mV p-p

ANALOG

INPUT

CLK IN

2

8 10k

AD783

50

7

ONE -

SHOT

18 +VIN HI

19 +VIN LOW

16 –VIN HI

17 –VIN LOW

AD670

21 R/W

Figure 8. AD783 to AD670 Interface

AD783 to AD671 (12-Bit, 500 ns ADC) Interface

The AD783 to AD671 interface requires an op amp, a dual

flip-flop, and a monostable multivibrator or “one-shot.” The

op amp amplifies the ± 2.5 V output of the AD783 to the

full-scale input of the AD671. Appropriate op amps include the

AD841 and AD845 (see the AD671 data sheet for additional

information). The flip-flops and one-shot are used to generate

the AD671 ENCODE pulse and the appropriately timed

AD783 S/H pulse.

A master sampling clock is tied to the clock input of flip-flop1

and the input of the one-shot. The D1 input of flip-flop1

should be tied high and the one-shot should be configured to

generate a pulse on a rising edge of the sampling clock. The ris-

ing edge of the sampling clock causes the Q1 output of the

flip-flop to go low placing the AD783 into hold mode. Simulta-

neously, a low going pulse is generated at the one-shot output.

The length of this pulse would usually be made long enough to

allow the output of the AD783 to settle (hold-mode settling

time), but because of the error-correcting ability of the AD671,

the length of this pulse may be reduced to approximately 200 ns.

–8–

REV. B

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