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AD7822 查看數據表(PDF) - Analog Devices

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AD7822 Datasheet PDF : 20 Pages
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AD7822/AD7825/AD7829
Figure 16 shows how to power up the AD7822 or AD7825 when
VDD is first connected or after the ADCs have been powered
down using the PD pin, or the CONVST pin, with either the
on-chip or an external reference. When the supplies are first
connected or after the part has been powered down by the PD
pin, only a rising edge on the PD pin will cause the part to
power up. When the part has been powered down using the
CONVST pin, a rising edge on either the PD pin or the CONVST
pin will power the part up again.
As with the AD7829, when using an external reference with the
AD7822 or AD7825, the falling edge of CONVST may occur
before the required power-up time has elapsed, however, if this
is the case, the conversion will not be initiated on the falling edge
of CONVST, but rather at the moment when the part has powered
up completely, i.e., after 1 µs. If the falling edge of CONVST
occurs after the required power-up time has elapsed, it is upon
this falling edge that a conversion is initiated. When using the
on-chip reference, it is necessary to wait the required power-
up time of approximately 25 µs before initiating a conversion;
i.e., a falling edge on CONVST may not occur before the
required power-up time has elapsed, when supplies are first
connected to the AD7822 or AD7825, or when the ADCs have
been powered down using the PD pin or the CONVST pin as
shown in Figure 16.
VDD
PD
CONVST
EXTERNAL REFERENCE
tPOWER-UP
1s
tPOWER-UP
1s
CONVST
tPOWER-UP tCONVERT
1s
330ns
POWER-DOWN
tCYCLE
10s @ 100kSPS
Figure 17. Automatic Power-Down
For example, if the AD7822 is operated in a continuous sam-
pling mode, with a throughput rate of 100 kSPS and using an
external reference, the power consumption is calculated as fol-
lows. The power dissipation during normal operation is 36 mW,
VDD = 3 V. If the power-up time is 1 µs and the conversion time
is 330 ns (@ +25°C), the AD7822 can be said to dissipate
36 mW (maximum) for 1.33 µs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 µs
and the average power dissipated during each cycle is (1.33/10)
× (36 mW) = 4.79 mW. This calculation uses the minimum
conversion time, thus giving the best case power dissipation
at this throughput rate. However, the actual power dissi-
pated during each conversion cycle could increase depending
on the actual conversion time (up to a maximum of 420 ns).
Figure 18 shows the power vs. throughput rate for automatic
full power-down.
100
10
1
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
VDD
PD
CONVST
ON-CHIP REFERENCE
tPOWER-UP
25s
tPOWER-UP
25s
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
Figure 16. AD7822/AD7825 Power-Up Time
POWER VS. THROUGHPUT
Superior power performance can be achieved by using the auto-
matic power-down (Mode 2) at the end of a conversion—see
Operating Modes section of the data sheet.
Figure 17 shows how the automatic power-down is implemented
using the CONVST signal to achieve the optimum power per-
formance for the AD7822, AD7825, and AD7829. The duration
of the CONVST pulse is set to be equal to or less than the
power-up time of the devices—see Operating Modes section. As
the throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
drops accordingly.
0.1
0
0 50 100 150 200 250 300 350 400 450 500
THROUGHPUT kSPS
Figure 18. AD7822/AD7825/AD7829 Power vs. Throughput
0
2048 POINT FFT
10
SAMPLING
2MSPS
fIN = 200kHz
20
30
40
50
60
70
80
FREQUENCY kHz
Figure 19. AD7822/AD7825/AD7829 SNR
REV. B
11

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