M68Z512 查看數據表（PDF） - STMicroelectronics

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M68Z512

4 Mbit (512 Kbit x 8) Low Power SRAM with Output Enable

STMicroelectronics 

M68Z512

READ Mode

The M68Z512 is in the READ mode whenever

Write Enable (W) is High with Output Enable (G)

Low, and Chip Enable (E) is asserted. This pro-

vides access to data from eight of the 4,194,304

locations in the static memory array, specified by

the 19 address inputs. Valid data will be available

at the eight output pins within tAVQV after the last

stable address, providing G is Low and E is Low.

If Chip Enable or Output Enable access times are

not met, data access will be measured from the

limiting parameter (tELQV or tGLQV) rather than the

address. Data out may be indeterminate at tELQX

and tGLQX, but data lines will always be valid at

tAVQV.

Figure 6. Address Controlled, READ Mode AC Waveforms

A0-A18

tAVAV

VALID

tAVQV

tAXQX

DQ0-DQ7

DATA VALID

Note: E = Low, E2 = High, +G = Low, W = High.

AI03034

Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms

A0-A18

E

G

DQ0-DQ7

tAVQV

tELQV

tAVAV

VALID

tELQX

tGLQV

tGLQX

tAXQX

tEHQZ

tGHQZ

VALID

Note: Write Enable (W) = High.

AI03035

Figure 8. Standby Mode AC Waveforms

E

ICC1

ICC2

tPU

50%

tPD

AI03036

7/15

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