ADG701 查看數據表（PDF） - Analog Devices

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ADG701

CMOS Low Voltage 2 V SPST Switches

Analog Devices 

PIN CONFIGURATIONS

8-Lead ␮SOIC

(RM-8)

D1

8S

NC 2

ADG701/

ADG702

7 GND

NC 3 TOP VIEW 6 IN

VDD 4 (Not to Scale) 5 NC

NC = NO CONNECT

6-Lead Plastic Surface Mount (SOT-23)

(RT-6)

D1

6 VDD

ADG701/

S 2 ADG702 5 NC

GND 3 TOP VIEW 4 IN

(Not to Scale)

NC = NO CONNECT

ADG701/ADG702

TERMINOLOGY

VDD

GND

S

D

IN

RON

RFLAT(ON)

IS (OFF)

ID (OFF)

ID, IS (ON)

VD (VS)

CS (OFF)

CD (OFF)

CD, CS (ON)

tON

tOFF

Off Isolation

Charge

Injection

Bandwidth

On Response

On Loss

Most Positive Power Supply Potential.

Ground (0 V) Reference.

Source Terminal. May be an input or output.

Drain Terminal. May be an input or output.

Logic Control Input.

Ohmic Resistance Between D and S.

Flatness is defined as the difference between

the maximum and minimum value of on

resistance as measured over the specified

analog signal range.

Source Leakage Current with the Switch “OFF.”

Drain Leakage Current with the Switch “OFF.”

Channel Leakage Current with the Switch “ON.”

Analog Voltage on Terminals D, S.

“OFF” Switch Source Capacitance.

“OFF” Switch Drain Capacitance.

“ON” Switch Capacitance.

Delay between applying the digital control

input and the output switching on. See Test

Circuit 4.

Delay between applying the digital control

input and the output switching off.

A measure of Unwanted Signal Coupling

Through an “OFF” Switch.

A measure of the glitch impulse transferred

from the digital input to the analog output

during switching.

The frequency at which the output is attenu-

ated by –3 dBs.

The frequency response of the “ON” switch.

The voltage drop across the “ON” switch seen

on the On Response vs. Frequency plot as how

many dBs the signal is away from 0 dB at very

low frequencies.

REV. A

–5–

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