LF3370 查看數據表（PDF） - LOGIC Devices

零件编号

产品描述 (功能)

生产厂家

LF3370

High-Definition Video Format Converter

LOGIC Devices 

DEVICES INCORPORATED

LF3370

High-Definition Video Format Converter

FIGURE 13. RSL CIRCUITRY

corresponding output peak is 35 clock

cycles.

R3

2

RSL1-0

R0

S3

UL3

UL0

S0

LL3

LL0

20

From Core

20

20

ROUND

13

13

SELECT

13

13

13

LIMIT

TABLE 2. SELECT FORMATS

SLCT1-0 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

00

F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4

01

F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5

10

F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6

11

F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7

plier by setting bit 4 in Configuration

Register 0 (see Table 5). The maximum

input and output clock rate this section

can operate at is the CLK rate. The total

internal pipeline latency from the input to

the output of this section (including RSL

circuitry) as shown in Figure 12 is 6 cycles.

To perform interpolation, the input data

rate of this section will be half of CLK rate.

Please note the maximum output data

rate is the CLK rate. To perform decima-

tion, the output data rate of this section

will be half of the input data rate. One

output sample is obtained for every two

input samples.

Once an impulse is clocked into the Half-

Band Filter section, the 55-value output

response begins after 8 clock cycles and

ends after 62 clock cycles. The pipeline

latency from the input of an impulse to its

The input/output formats are always in

two’s complement format as shown in

Figure 3. In Interpolate Mode, the gain of

the Half-Band Filter is halved (due to half

of the input samples being padded with

zeros). A right shifted Select window is

required to maintain an overall filter gain

of 1. It is possible that ringing on the

filter’s output could cause the high order

bit (bit F18 in Figure 3 - Interpolate Filter

Output Bit Weighting) to become HIGH. If

a right shifted Select window is used, this

F18 bit becomes the sign bit of the Selected

window – and the output is erroneously

considered negative. To ensure that no

overflow conditions occur, an internal

Limiter within each Half-Band Filter

monitors its output. During Interpolate

mode, this Limiter clamps the output word

to 3FFFFH (20-bit maximum positive value

) 2) or C0000H (20-bit maximum negative

value ) 2) if a positive or negative overflow

occurs respectively. The internal 24-bits of

the Half-Band Filter are truncated to 20-

bits and then passed to the Round section

of the RSL circuitry; see RSL section for

further details. This section is fully

bypassable by use of programmable

delays (see Bypass Options section for

further details).

FIGURE 14. FREQUENCY RESPONSE OF FILTER

0

–10

–20

–30

–40

–50

–60

–70

–80

0

0.1ƒS

0.2ƒS

0.3ƒS

0.4ƒS

0.5ƒS

Look-Up Table

Three optional programmable Input/

Output 1K x 13-bit LUTs have been

provided for Channels A, B, and C for

various uses such as Gamma Correction.

There are NOT actually two LUTs per

channel as shown in Figures 1 and 2; only

one LUT per channel can be selected for

use at any given time. The latency

through a LUT section is 2 cycles. This

latency is present on the datapath regard-

less of whether the LUT is in use or not.

When using a LUT, the appropriate

addressed value will be passed as an

FREQUENCY (NORMALIZED)

Video Imaging Products

11

03/13/2001–LDS.3370-F

Share Link: