LF3370 查看數據表（PDF） - LOGIC Devices
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LF3370 Datasheet PDF : 24 Pages
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DEVICES INCORPORATED
LF3370
High-Definition Video Format Converter
halfband filters to the data flowing
through the LF3370. A latched HIGH to
LOW transition on SYNC control signal is
needed to initialize the device to mark the
beginning of valid data.
In addition, if 4:2:2 interleaved video data
is desired for input or output, a HIGH to
LOW transition on SYNC must be
registered by a simultaneous rising edge of
CLK and CLK/2. CLK/2 is an internal
clock that must be synchronized to CLK
by use of RESET only if the core is running
at half the rate of CLK (see RESET
discussio n and Figures 4 & 5).
Furthermore, SYNC is used to identify one
interleaved data set from another. For
example, in the case of interleaved
Chroma, Cb and Cr samples must be
properly demultiplexed and synchro-
nized for processing.
To differentiate a Cb sample from Cr, there
needs to be a HIGH to LOW transition on
SYNC on the first Cb sample (see Figure 4
& 5); SYNC can also be toggled on every
Cb sample for re-synchronization.
In the case that Cb is the first valid data
word, SYNC may be used only once in
device initialization and kept low until re-
synchronization is desired. Therefore,
when there is a HIGH to LOW transition
on SYNC, the following is assumed: Cb
will occur on the first LOW on SYNC that
is latched, Cb will occur every two clock
cycles if interleaved Chroma is presented
to the input port B12-0, Cb will occur every
4 clock cycles if single channel 4:2:2
interleaved video is presented to the input
port A12-0.
SYNC control signal is also used to
synchronize the interpolation/decimation
output data from the Half-Band Filter to
the Output Multiplexer. This synchroniza-
tion is done automatically.
RESET
RESET should be used when initializing
the device for proper operation. It is used
to synchronize the LF3370 core clock to
the master clock. In the case that single
channel 4:2:2 interleaved video data is
desired either on the input or output, thus
using only one input or one output port
(not including Key data), the internal
clock rate will be half (CLK/2) of the
master clock rate (CLK). In this case,
RESET is needed to synchronize the rising
edge of CLK/2 to a known rising edge of
CLK (see Figure 4). For example, after
configuring the LF3370 and before
FIGURE 8. INPUT BIAS
R3
R0
2
INBIAS1-0
13
13
From Input Demux
13
13
FIGURE 9. OUTPUT BIAS
R3
R0
2
OUTBIAS1-0
13
From Core
13
13
streaming valid data through the part, a
RESET event should be used to align the
clock edges (see Figure 4 & 5).
Furthermore, RESET will clear HF0 and
HF1. A LOW state detected on RESET on a
rising edge of clock will clear flags HF0
and HF1 on the following rising edge of
clock. Please note HBLANK should be
FIGURE 10. HBLANK AND COUNTER
CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
16
17
18
HBLANK
20-bit
COUNTER
HF0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
HF1
A'12-0*
DN HBLANK Word A DN+3 DN+4 DN+5 DN+6 DN+7 DN+8 DN+9 DN+10 DN+11
HBLANK Word A
B'12-0*
DN HBLANK Word B DN+3 DN+4 DN+5 DN+6 DN+7 DN+8 DN+9 DN+10 DN+11
HBLANK Word B
C'12-0*
DN HBLANK Word C DN+3 DN+4 DN+5 DN+6 DN+7 DN+8 DN+9 DN+10 DN+11
HBLANK Word C
D'12-0*
DN HBLANK Word D DN+3 DN+4 DN+5 DN+6 DN+7 DN+8 DN+9 DN+10 DN+11
HBLANK Word D
* Data values at output of Input LUT section
In this example, HF0 Count Value is set to 3 and HF1 Count Value is set to 5
Video Imaging Products
8
03/13/2001–LDS.3370-F
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