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AD14160LKB-4

Quad-SHARC DSP Multiprocessor

Analog Devices 

AD14160/AD14160L

DETAILED DESCRIPTION

is a 10-port, 32-register (16 primary, 16 secondary) file. Each

Architectural Features

SHARC’s core also implements two data address generators

ADSP-21060 Core

(DAGs), implementing circular data buffers in hardware. The

The AD14160/AD14160L is based on the powerful ADSP-21060 DAGs contain sufficient registers to allow the creation of up to

(SHARC) DSP chip. The ADSP-21060 SHARC combines a

32 circular buffers. The 48-bit instruction word accommodates a

high performance floating-point DSP core with integrated, on- variety of parallel operations, for concise programming. For ex-

chip system features including a 4 Mbit SRAM memory, host

ample, the ADSP-21060 can conditionally execute a multiply, an

processor interface, DMA controller, serial ports, and both link add, a subtract, and a branch, all in a single instruction.

port and parallel bus connectivity for glueless DSP multiprocess- The SHARCs contain 4 Mbits of on-chip SRAM each, orga-

ing, (see Figure 1). It is fabricated in a high speed, low power

nized as two blocks of 2 Mbits, which can be configured for

CMOS process, and has a 25 ns instruction cycle time. The arith- different combinations of code and data storage. The memory

metic/ logic unit (ALU), multiplier and shifter all perform single- can be configured as a maximum of 128K words of 32-bit data,

cycle instructions, and the three units are arranged in parallel,

256K words of 16-bit data, 80K words of 48-bit instructions (or

OBSOLETE maximizing computational throughput.

The SHARC features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data, and the pro-

gram memory (PM) bus transfers both instructions and data.

There is also an on-chip instruction cache which selectively

caches only those instructions whose fetches conflict with the

PM bus data accesses. This combines with the separate program

and data memory buses to enable three-bus operation for fetch-

ing an instruction and two operands, all in a single cycle. The

SHARC also contains a general purpose data register file, which

40-bit data), or combinations of different word sizes up to

4 megabits. A 16-bit floating-point storage format is supported

which effectively doubles the amount of data that may be stored

on chip. Conversion between the 32-bit floating point and 16-

bit floating point formats is done in a single instruction. Each

memory block is dual-ported for single-cycle, independent

accesses by the core processor and I/O processor or DMA con-

troller. The dual-ported memory and separate on-chip buses

allow two data transfers from the core and one from I/O, all in a

single cycle.

CORE PROCESSOR

TIMER INSTRUCTION

CACHE

32 x 48-BIT

DAG1 DAG2

PROGRAM

DUAL-PORTED SRAM

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT

ADDR

DATA

ADDR

DATA

I/O PORT

DATA

ADDR

DATA

ADDR

JTAG 7

TEST AND

EMULATION

8 x 4 x 32 8 x 4 x 24

SEQUENCER

EXTERNAL

PM ADDRESS BUS

24

IOD

IOA

48

17

PORT

DM ADDRESS BUS 32

32

ADDR BUS

MUX

BUS

CONNECT

(PX)

PM DATA BUS 48

DM DATA BUS 40/32

MULTIPROCESSOR

INTERFACE

48

DATA BUS

MUX

HOST PORT

MULTIPLIER

DATA

REGISTER

FILE

16 x 40-BIT

BARREL

SHIFTER

ALU

DMA

4

IOP

CONTROLLER

REGISTERS

6

(MEMORY MAPPED)

SERIAL PORTS

CONTROL,

(2)

6

STATUS, AND

LINK PORTS

36

DATA BUFFERS

(6)

I/O PROCESSOR

Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14160/AD14160L)

–2–

REV. A

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