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AD14160LKB-4

Quad-SHARC DSP Multiprocessor

Analog Devices 

AD14160/AD14160L

Shared Memory Multiprocessing

The bus master can communicate with slave SHARCs by writ-

The AD14160/AD14160L takes advantage of the powerful

ing messages to their internal IOP registers. The MSRG0–

multiprocessing features built into the SHARC. The SHARCs are MSRG7 registers are general-purpose registers that can be used

connected to maximize the performance of this cluster-of-four

for convenient message passing, semaphores and resource shar-

architecture, and still allow for off-module expansion. The

ing between the SHARCs. For message passing, the master

AD14160/AD14160L in itself is a complete shared memory

communicates with a slave by writing and/or reading any of the

multiprocessing system, as shown in Figure 3. The unified ad-

eight message registers on the slave. For vector interrupts, the

dress space of the SHARCs allows direct interprocessor ac-

master can issue a vector interrupt to a slave by writing the

cesses of each SHARCs’ internal memory. In other words, each address of an interrupt service routine to the slave’s VIRPT

SHARC can directly access the internal memory and IOP registers register. This causes an immediate high priority interrupt on the

of each of the other SHARCs by simply reading or writing to the slave which, when serviced, will cause it to branch to the speci-

appropriate address in multi-processor memory space (see Fig- fied service routine.

ure 2)—this is called a direct read or direct write.

Off-Module Memory and Peripherals Interface

OBSOLETE Bus arbitration is accomplished with the on-SHARC arbitration

logic. Each SHARC has a unique ID, and drives the Bus-Request

(BR) line corresponding to its ID, while monitoring all others.

BR1–BR4 are used within the AD14160/AD14160L, while BR5

and BR6 can be used for expansion. All bus requests (BR1–BR6)

are included in the module I/O.

Two different priority schemes, fixed and rotating, are available

to resolve competing bus requests. The RPBA pin selects which

scheme is used: when RPBA is high, rotating priority bus arbitra-

tion is selected, and when RPBA is low, fixed priority is selected.

Table I. Rotating Priority Arbitration Example

Cycle ID1

1

M

2

4

3

4

Hardware Processor IDs

ID2 ID3 ID4 ID5 ID6

1

2 BR 3 4 5

5 BR M-BR 1 2 3

5 BR M

1 23

Initial Priority Assignments

The AD14160/AD14160L’s external port provides the interface to

off-module memory and peripherals (see Figure 5). This port

consists of the complete external port bus of the SHARC, bused

together in common among the four SHARCs.

The 4-gigaword off-module address space is included in the

AD14160/AD14160L’s unified address space. Addressing of

external memory devices is facilitated by each SHARC inter-

nally decoding the high order address lines to generate memory

bank select signals. Separate control lines are also generated for

simplified addressing of page-mode DRAM. The AD14160/

AD14160L also supports programmable memory wait states and

external memory acknowledge controls to allow interfacing to

DRAM and peripherals with variable access, hold and disable

time requirements.

Link Port I/O

Each individual SHARC features six 4-bit link ports that facili-

tate SHARC-to-SHARC communication and external I/O inter-

4

5 BR M 1

2 3 4 BR

facing. Each link port can be configured for either 1× or 2×

5

1 BR 2

3

4 5 M Final Priority Assignments operation, allowing each to transfer either 4 or 8 bits per cycle.

NOTES

1–5 = Assigned Priority.

M = Bus Mastership (in that cycle).

BR = Requesting Bus Mastership with BRx.

The link ports can operate independently and simultaneously,

with a maximum bandwidth of 40 MBytes/s each, or a total of

240 MBytes/s per SHARC.

Bus mastership is passed from one SHARC to another during a

bus transition cycle. A bus transition cycle only occurs when the

current bus master deasserts its BR line and one of the slave

SHARCs asserts its BR line. The bus master can therefore re-

tain bus mastership by keeping its BR line asserted. When the

bus master deasserts its BR line, and no other BR line is as-

serted, then the master will not lose any bus cycles. When more

The AD14160/AD14160L provides additional link port I/O

beyond that of the AD14060. Internally, two links from each

SHARC form a ring connection among the four. The remaining

four link ports from each SHARC are brought out indepen-

dently from each SHARC. A maximum of 640 MBytes/s link

port bandwidth is then available off of the AD14160/AD14160L.

The link port connections are detailed in Figure 4.

than one SHARC asserts its BR line, the SHARC with the

highest priority request becomes bus master on the following

cycle. Each SHARC observes all of the BR lines, and therefore

tracks when a bus transition cycle has occurred, and which

processor has become the new bus master. Master processor

changeover incurs only one cycle of overhead. An example bus

transition sequence is shown in Table I.

1

2

3 SHARC_A

4

55

1

2

SHARC_B 3

4

Bus locking is possible, allowing indivisible read-modify-write

sequences for semaphores. In either the fixed or rotating priority

scheme, it is also possible to limit the number of cycles the

master can control the bus. The AD14160/AD14160L also

provides the option of using the Core Priority Access (CPA)

mode of the SHARC. Using the CPA signal allows external bus

accesses by the core processor of a slave SHARC to take priority

over ongoing DMA transfers. Also, each SHARC can broadcast

write to all other SHARCs simultaneously, allowing the implemen-

tation of reflective semaphores.

0

0

1

2

3 SHARC_D

4

55

0

0

1

2

SHARC_C 3

4

Figure 4. Link Port Connections

–4–

REV. A

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