IDT54827CE 查看數據表（PDF） - Integrated Device Technology
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IDT54827CE Datasheet PDF : 7 Pages
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IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
PIN CONFIGURATION
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
CLR 11
GND 12
24
VCC
23
Y0
22
Y1
21
Y2
20
Y3
19
Y4
18
Y5
17
Y6
16
Y7
15
Y8
14 EN
13 CP
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
43 2
28 27 26
D2
5
1
25
Y2
D3
6
24
Y3
D4
7
23
Y4
NC 8
22
NC
D5
9
21
Y5
D6
10
20
Y6
D7
11
19
Y7
12 13 14 15 16 17 18
CERDIP/ SOIC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating
Commercial Military Unit
VTERM(2) Terminal Voltage
–0.5 to +7 –0.5 to +7 V
with Respect to GND
VTERM(3) Terminal Voltage
–0.5 to VCC –0.5 to VCC V
with Respect to GND
TA
Operating Temperature
0 to +70 –55 to +125 °C
TBIAS
Temperature under BIAS –55 to +125 –65 to +135 °C
TSTG
Storage Temperature
–55 to +125 –65 to +150 °C
PT
Power Dissipation
0.5
0.5
W
IOUT
DC Output Current
120
120
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
6
10 pF
COUT
Output Capacitance VOUT = 0V
8
12 pF
NOTE:
1. This parameter is measured at characterization but not tested.
LCC
TOP VIEW
LOGIC SYMBOL
9
D
D
Q
CP EN CLR
CP
EN
CLR
OE
9
Y
PIN DESCRIPTION
Pin Name I/O
Description
Dx
I
D flip-flop data inputs
CLR
I
For both inverting and non-inverting registers, when
the clear input is LOW and OE is LOW, the Qx
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.
CP
I
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Yx
O Register 3-state outputs
EN
I
Clock Enable. When the clock enable is LOW, data
on the DI input is transferred to the QI output on the
LOW-to-HIGH clock transition. When the clock enable
is HIGH, the QI outputs do not change state,
regardless of the data or clock input transitions.
OE
I
Output Control. When the OE input is HIGH, the Yx
outputs are in the high impedance state. When the OE
input is LOW, the TRUE register data is present at the
Yx outputs.
2
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