IDT70V07L(1996) 查看數據表（PDF） - Integrated Device Technology

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IDT70V07L
(Rev.:1996)

HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V07S/L

HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)

A0-A2

SEM

I/O0

R/W

OE

VALID ADDRESS

tAW

tWR

tEW

tDW

DATAIN

VALID

tAS

tWP

tDH

tSAA

tOH

VALID ADDRESS

tACE

tSOP

DATAOUT

VALID(2)

tSWRD

tAOE

Write Cycle

Read Cycle

2943 drw 11

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.

TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)

A0"A"-A2"A"

SIDE(2) “A”

W R/ "A"

MATCH

SEM"A"

A0"B"-A2"B"

SIDE(2) “B”

W R/ "B"

tSPS

MATCH

SEM"B"

2943 drw 12

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from W R/ "A" or SEM"A" going HIGH to R/WB or SEM"B" going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

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