IDT707288L25PF 查看數據表（PDF） - Integrated Device Technology

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IDT707288L25PF

HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

Integrated Device Technology 

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM

Description

The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-Switchable

Dual-Ported SRAM organized into four independent 16K x 16 banks. The

device has two independent ports with separate control, address, and

I/O pins for each port, allowing each port to asynchronously access

any 16K x 16 memory block not already accessed by the other port.

Accesses by the ports into specific banks are controlled via bank select pin

inputs under the user's control. Mailboxes are provided to allow inter-

processor communication. Interrupts are provided to indicate mailbox

writes have occurred. An automatic power down feature controlled by

the chip enables (CE0 and CE1) permits the on-chip circuitry of each port

to enter a very low standby power mode and allows fast depth expansion.

The IDT707288 offers a maximum address-to-data access time as fast

as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP).

Functionality

The IDT707288 is a high-speed asynchronous 64K x 16 Bank-

Switchable Dual-Ported SRAM, organized in four 16K x 16 banks. The

two ports are permitted independent, simultaneous access into separate

banks within the shared array. There are four user-controlled Bank Select

input pins, and each of these pins is associated with a specific bank within

the memory array. Access to a specific bank is gained by placing the

associated Bank Select pin in the appropriate state: VIH assigns the bank

to the left port, and VIL assigns the bank to the right port (See Truth Table

Industrial and Commercial Temperature Ranges

IV). Once a bank is assigned to a particular port, the port has full access

to read and write within that bank. Each port can be assigned as many

banks within the array as needed, up to and including all four banks.

The IDT707288 provides mailboxes to allow inter-processor commu-

nication. Each port has four 16-bit mailbox registers available to which it

can write and read and which the opposite port can read only. These

mailboxes are external to the common SRAM array, and are accessed

by setting MBSEL = VIL while setting CE = VIH. Each mailbox has an

associated interrupt: a port can generate an interrupt to the opposite port

by writing to the upper byte of any one of its four 16-bit mailboxes. The

interrupted port can clear the interrupt by reading the upper byte. This read

will not alter the contents of the mailbox.

If desired, any source of interrupt can be independently masked via

software. Two registers are provided to permit interpretation of interrupts:

the Interrupt Cause Register and the Interrupt Status Register. The

Interrupt Cause Register gives the user a snapshot of what has caused

the interrupt to be generated - the specific mailbox written to. The

information in this register provides post-mask signals: interrupt sources

that have been masked will not be updated. The Interrupt Status Register

gives the user the status of all bits that could potentially cause an interrupt

regardless of whether they have been masked. Truth Table V gives a

detailed explanation of the use of these registers.

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