IDT707288S20G 查看數據表（PDF） - Integrated Device Technology
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IDT707288S20G
Integrated Device Technology
IDT707288S20G Datasheet PDF : 16 Pages
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IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Pin Configurations(1,2,3)
INDEX
Industrial and Commercial Temperature Ranges
A6L
A7L
A8L
A9L
A10L
A11L
A13L
NC
BKSEL0
LBL
UBL
CE0L
CE1L
MBSELL
Vcc
R/WL
OEL
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
1100 99
98
97 96 95
94
93
92
91 90
89
88
87
86
85 84
83
82
81
80
79
78 77
76
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
11
IDT707288PF
PN100-1(4)
66
65
12
64
13
100-Pin TQFP
63
14
Top View(5)
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6R
A7R
A8R
A9R
A10R
A11R
A13R
NC
BKSEL3
LBR
UBR
CE0R
CE1R
MBSELR
GND
R/WR
OER
GND
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
3592 drw 02 ,
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
A0 - A13(1,6)
Address Inputs
BA0 - BA1(1)
Bank Address Inputs
MBSEL(1)
Mailbox Access Control Gate
BKSEL0-3(2)
Bank Select Inputs
R/W(1)
Read/Write Enable
OE(1)
Output Enable
CE0, CE1(1)
Chip Enables
UB, LB(1)
I/O Byte Enables
I/O0 - I/O15(1)
Bidirectional Data Input/Output
INT(1)
Interrupt Flag (Output)(3)
VCC(4)
+5VPower
GND(5)
Ground
NOTES:
3592 tbl 01
1. Duplicated per port.
2. Each bank has an input pin assigned that allows the user to toggle the assignment
of that bank between the two ports. Refer to Truth Table IV for more details. When
changing the bank assignments, accesses of the affected banks must be
suspended. Accesses may continue uninterrupted in banks that are not being
reallocted.
3. Generated upon mailbox access.
4. All Vcc pins must be connected to power supply.
5. All GND pins must be connected to ground supply.
6. The first six address pins (A0-A5) for each port serve dual functions. When MBSEL
= VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins
serve as mailbox address inputs (A6-A13 are ignored).
6.342
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