IDT707288S15PFI 查看數據表（PDF） - Integrated Device Technology
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IDT707288S15PFI
Integrated Device Technology
IDT707288S15PFI Datasheet PDF : 16 Pages
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IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Truth Table I Chip Enable(1,2,3,4)
Industrial and Commercial Temperature Ranges
CE
CE0
CE1
Mode
VIL
VIH
Port Selected (TTL Active)
L
< 0.2V
>VCC -0.2V
Port Selected (CMOS Active)
VIH
X
Port Deselected (TTL Inactive)
H
X
>VCC -0.2V
VIL
Port Deselected (TTL Inactive)
X
Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.
2. Port "A" and "B" references are located where CE is used.
3. "H" = VIH and "L" = VIL.
4. CE and MBSEL cannot both be active at the same time.
3592 tbl 02
Truth Table II Non-Contention Read/Write Control
Inputs(1)
Outputs
CE(2)
R/W
OE
UB
LB
MBSEL
I/O8-15
I/O0-7
Mode
H
X
X
X
X
H
High-Z
High-Z Deselcted: Power-Down
X(3)
X
X
H
H
X(3)
High-Z
High-Z Both Bytes Deselected
L
L
X
L
H
H
DATAIN
High-Z Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATAIN Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN Write to Both Bytes
L
H
L
L
H
H
DATAOUT
High-Z Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATAOUT Read Lower Byte Only
L
H
L
L
L
H
DATAOUT
DATAOUT Read Both Bytes
X(3)
X
H
X
X
X(3)
High-Z
High-Z Outputs Disabled
NOTES:
1. BA0L - BA1L ≠ BA0R - BA1R: cannot access same bank simultaneously from both ports.
2. Refer to Truth Table I.
3. CE and MBSEL cannot both be active at the same time.
3592 tbl 03
Truth Table III Mailbox Read/Write Control(1)
Inputs
Outputs
CE(2)
R/W
OE
UB
LB
MBSEL
I/O8-15
I/O0-7
Mode
H
H
L
X(3)
X(3)
L
DATAOUT DATAOUT Read Data from Mailbox, ↓ clears interrupt
H
H
L
L
L
L
DATAOUT DATAOUT Read Data from Mailbox, ↓ clears interrupt
H
L
X
L(3)
L(3)
L
DATAIN
DATAIN Write Data into Mailbox
L
X
X
X
X
L
____
____
Not Allowed
NOTES:
3592 tbl 04
1. There are four mailbox locations per port written to and read from all the I/O's (I/O0-I/O15). These four mailboxes are addressed by A0-A5. Refer to Truth Table V.
2. Refer to Truth Table I.
3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to UB and LB appropriately.
6.4 2
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