IDT707288S25PFI 查看數據表（PDF） - Integrated Device Technology

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IDT707288S25PFI

HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

Integrated Device Technology 

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM

Assigning the Banks via the

External Bank Selects

There are four bank select pins available on the IDT707288, and each

of these pins is associated with a specific bank within the memory array.

The pins are user-controlled inputs: access to a specific bank is assigned

to a particular port by setting the input to the appropriate level. The process

of assigning the banks is detailed in Truth Table IV. Once a bank is assigned

to a port, the owning port has full access to read and write within that bank.

The opposite port is unable to access that bank until the user reassigns the

port. Access by a port to a bank which it does not control will have no effect

Industrial and Commercial Temperature Ranges

if written, and if read unknown values on D0-D15 will be returned. Each

port can be assigned as many banks within the array as needed, up to

and including all four banks.

The bank select pin inputs must be set at either VIH or VIL - these inputs

are not tri-statable. When changing the bankassignments, accesses of the

affected banks must be suspended. Accesses may continue uninterrupted

in banks that are not being reallocated.

Truth Table IV – Memory Bank

Assignment (CE = VIH)(2,3)

BKSEL0 BKSEL1 BKSEL2 BKSEL3

BANK AND

DIRECTION(1)

H

X

X

X

BANK 0 LEFT

X

H

X

X

BANK 1 LEFT

X

X

H

X

BANK 2 LEFT

X

X

X

H

BANK 3 LEFT

L

X

X

X

BANK 0 RIGHT

X

L

X

X

BANK 1 RIGHT

X

X

L

X

BANK 2 RIGHT

X

X

X

L

BANK 3 RIGHT

NOTES:

3592 tbl 13

1 . Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second 16Kx16

memory spaces, Bank 2 to the third 16Kx16 memory spaces, and Bank 3

to the fourth 16Kx16 memory spaces. 'LEFT' indicates the bank is assigned

to the left port; 'RIGHT' indicates the bank is assigned to the right port. 0-4 banks

may be assigned to either port.

2 . The bank select pin inputs must be set at either VIH or VIL - these inputs are not

tri-statable. When changing the bank assignments, accesses of the affected

banks must be suspended. Accesses may continue uninterrupted in banks that

are not beign reallocated.

3 . 'H' = VIH, 'L' = VIL, 'X' = Don't Care.

Mailbox Interrupts and Interrupt

Control Registers

If the user chooses the mailbox interrupt function, four mailbox locations

are assigned to each port. These mailbox locations are external to the

memory array. The mailboxes are accessed by setting MBSEL = VIL

while holding CE = VIH.

The mailboxes are 16 bits wide and controllable by byte: the message

is user-defined since these are addressable SRAM locations. An interrupt

is generated to the opposite port upon writing to the upper byte of any

mailbox location. A port can read the message it has just written in order

to verify it: this read will not alter the status of the interrupt sent to the opposite

port. The interrupted port can clear the interrupt by reading the upper byte

of the applicable mailbox. This read will not alter the contents of the mailbox.

The use of mailboxes to generate interrupts to the opposite port and the

reading of mailboxes to clear interrupts is detailed in Truth Table V.

If desired, any of the mailbox interrupts can be independently masked

via software. Masking of the interrupt sources is done in the Mask Register.

The masks are individual and independent: a port can mask any

combination of interrupt sources with no effect on the other sources. Each

port can modify only its own Mask Register. The use of this register is

detailed in Truth Table V.

Two registers are provided to permit interpretation of interrupts: these

are the Interrupt Cause Register and the Interrupt Status Register. The

Interrupt Cause Register gives the user a snapshot of what has caused

the interrupt to be generated - the specific mailbox written to by the opposite

port. The information in this register provides post-mask signals: interrupt

sources that have been masked will not be updated. The Interrupt Status

Register gives the user the status of all bits that could potentially cause an

interrupt regardless of whether they have been masked. The use of the

Interrupt Cause Register and the Interrupt Status Register is detailed in

Truth Table V.

6.842

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