IDT707288L25G 查看數據表（PDF） - Integrated Device Technology
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IDT707288L25G
Integrated Device Technology
IDT707288L25G Datasheet PDF : 16 Pages
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IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V Mailbox Interrupts (CE = VIH)(8,9)
MB
SEL R/W UB LB A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DESCRIPTION
L X X X L L L L L L RESERVED (7)
RESERVED (7)
L
X
XX
•••
•••
•••
•••
•••
•••
RESERVED (7)
RESERVED (7)
L (1) (1) (1) H L L L L L X X X X X X X X X X X X X X X X MAILBOX 0 - SET INTERRUPT ON OPPOSITE PORT
L (1) (1) (1) H L L L L H X X X X X X X X X X X X X X X X MAILBOX 1 - SET INTERRUPT ON OPPOSITE PORT
L (1) (1) (1) H L L L H L X X X X X X X X X X X X X X X X MAILBOX 2 - SET INTERRUPT ON OPPOSITE PORT
L (1) (1) (1) H L L L H H X X X X X X X X X X X X X X X X MAILBOX 3 - SET INTERRUPT ON OPPOSITE PORT
↑ H (2) (2) H L L H L L X X X X X X X X X X X X X X X X MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT
↑ H (2) (2) H L L H L H X X X X X X X X X X X X X X X X MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT
↑ H (2) (2) H L L H H L X X X X X X X X X X X X X X X X MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT
↑ H (2) (2) H L L H H H X X X X X X X X X X X X X X X X MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT
L (3) (3) (3) H L H L L L (4) (4) (4) (4) (5) (5) (5) (5) (6) (6) (6) (6) X X X X MAILBOX INTERRUPT CONTROLS
L
X
XX
•
••
•
••
•
••
•
••
•
••
•
••
RESERVED (7)
RESERVED (7)
L X X X H H H H H H RESERVED (7)
RESERVED (7)
3592 tbl 14
NOTES:
1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in either 8-bit or
16-bit widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be individually masked if desired,
and the status of the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port can read its own mailboxes to verify the data
written, without affecting the interrupt which is sent to the opposite port.
2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a particular
mailbox clears the interrupt associated with that mailbox without modifying the data written. Once the address and R/W are stable, the actual clearing of the
interrupt is triggered by the transition of MBSEL from VIH to VIL.
3. This register contains the Mask Register (bits D0-D3), the Interrupt Cause Register (bits D4-D7), and the Interrupt Status Register (bits D8-D11). The controls for
R/W, UB, and LB are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D12-D15 are "Don't Care".
4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing VIH to the appropriate bit (D0 = Mailbox 0, D1 =
Mailbox 1, D2 = Mailbox 2, and D3 = Mailbox 3) disables the interrupt, while writing VIL enables the interrupt. All four bits in this register must be written at the
same time. This register can be read at any time to verify the mask settings. The masks are individual and independent: any single interrupt source can be
masked with no effect on the other sources. Each port can modify only its own mask settings.
5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading VOL for a specific bit (D4 =
Mailbox 0, D5 = Mailbox 1, D6 = Mailbox 2, and D7 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt. Acknowledging the
interrupt clears the bit in this register (see Note 2 for this table). This register provides post-mask information: if the interrupt source has been masked, the
associated bit in this register will not update.
6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of whether they
have been masked. Reading VOL for a specific bit (D8 = Mailbox 0, D9 = Mailbox 1, D10 = Mailbox 2, and D11 = Mailbox 3) indicates that the associated
interrupt source has generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for this table). This register provides
pre-mask information: regardless of whether an interrupt source has been masked, the associated bit in this register will update.
7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D0-D15 will be returned.
8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these registers.
9. 'L' = VIL or VOL, 'H' = VIH or VOH, 'X' = Don't Care.
6.942
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