IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSY (M/S = VIH)(2,4,5)
tWC
ADDR"A"
MATCH
tWP
W R/ "A"
DATAIN "A"
tAPS (1)
ADDR"B"
BUSY"B"
tDW
VALID
MATCH
tDH
tBDA
tBDD
tWDD
DATAOUT "B"
VALID
tDDD (3)
2954 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
W R/ "A"
BUSY"B"
tWP
tWB
tWH( 1 )
W R/ "B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.
2954 drw 14
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
6.12
13