IDT7015S17JB(1996) 查看數據表（PDF） - Integrated Device Technology
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IDT7015S17JB Datasheet PDF : 20 Pages
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IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
WAVEFORM OF INTERRUPT TIMING(1)
tWC
ADDR"A"
CE"A"
tAS(3)
INTERRUPT SET ADDRESS (2)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tWR (4)
W R/ "A"
INT"B"
tINS (3)
2954 drw 17
ADDR"B"
CE"B"
tAS (3)
tRC
INTERRUPT CLEAR ADDRESS (2)
OE"B"
tINR (3)
INT"B"
2954 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG(1)
R/WL
L
X
X
X
Left Port
CEL OEL A12L-A0L INTL
L
X 1FFF
X
X
X
X
X
X
X
X
L(3)
L
L
1FFE
H(2)
R/WR
X
X
L
X
Right Port
CER OER A12R-A0R INTR
X
X
X
L(2)
L
L
1FFF H(3)
L
X 1FFE X
X
X
X
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2954 tbl 15
6.12
15
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