IDT7015S17JB 查看數據表（PDF） - Integrated Device Technology
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IDT7015S17JB Datasheet PDF : 20 Pages
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HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
IDT7015S/L
Features:
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Commercial: 12/15/17/20/25/35ns (max.)
– Industrial: 20ns (max.)
– Military: 20/25/35ns (max.)
◆ Low-power operation
– IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆ IDT7015 easily expands data bus width to 18 bits or more
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
◆ M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
◆ Busy and Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-
pin TQFP
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts available, see ordering information
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O8L
BUSYL(1,2)
A12L
A0L
I/O
Control
I/O
Control
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(2)
M/S
NOTES:
1. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
1
©2006 Integrated Device Technology, Inc.
Address
Decoder
I/O0R-I/O8R
BUSYR(1,2)
A12R
A0R
CER
OER
R/WR
2954 drw 01
SEMR
INTR(2)
APRIL 2006
DSC 2954/7
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