IDT7015S17JGI 查看數據表（PDF） - Integrated Device Technology

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IDT7015S17JGI

HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7015S/L

High-Speed 8K x 9 Dual-Port Static RAM

Waveform of Read Cycles(5)

ADDR

CE

OE

tRC

tAA(4)

tACE(4)

tAOE (4)

Military, Industrial and Commercial Temperature Ranges

R/W

DATAOUT

tLZ (1)

tOH

VALID DATA(4)

tHZ(2)

BUSYOUT

tBDD(3,4)

2954 drw 07

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

read operations BUSY

Timing of Power-Up / Power-Down

CE

tPU

ICC

50%

ISB

tPD

50%

,

2954 drw 08

6.842

APRIL 04, 2006

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