CXA1843Q 查看數據表（PDF） - Sony Semiconductor

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CXA1843Q

High-Speed Sample-and-Hold IC

Sony Semiconductor 

CXA1843Q

Notes on Operation

(1) In circuit board layout, it is necessary that the AGND and DGND patterns be as large as possible and that

double or more layer pattern be used to make low impedance.

(2) To prevent digital system noise interference with the analog system, the AGND and DGND, AVCC and

DVCC, AVEE and DVEE on the PCB must be separated from each other. However, connect the AVEE and

DVEE with coil and others to prevent the generation of differential voltage.

(3) The AVCC, DVCC, AVEE and DVEE pins must be connected to the AGND or DGND respectively via ceramic

chip capacitors those are 0.1µF or more, as close to the pin as possible.

(4) The length of the wiring between the S/H SHOUT and A/D converter VIN should be as short as possible.

(5) The range of the signal input to VIN (Pin 3) of the sample-and-hold circuit is 0 to –2V.

(6) Adjust the VREFIN applied voltage so that VREFFB = f – 2V.

(7) As shown in the Block Diagram, the amplifier input and output are internally connected to the REFOUT

and REFFB pins. To generate REFFB voltage for the reference voltage of A/D converter, the connection

of an external PNP transistor (hFE ≥ 100 (typ.)) is required as shown in the Application Circuit.

(8) Make the S/H DVCC2 voltage equal to the A/D converter DVCC1 voltage.

–8–

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