ISL59112IEZ-T7(2005) 查看數據表（PDF） - Intersil
零件编号
产品描述 (功能)
生产厂家
ISL59112IEZ-T7 Datasheet PDF : 6 Pages
| |||
ISL59112
Electrical Specifications VS+ = 3.3V, VS- = GND, TA = 25°C, RL = 150Ω to GND, unless otherwise specified (Continued)
DESCRIPTION
PARAMETER
CONDITIONS
MIN TYP MAX
SR(hl)
tF
tR
Negative Slew Rate
Fall Time
Rise Time
VIN = 1VSTEP
1.0VSTEP
1.0VSTEP, 20% - 80%
-80
-30
9
9
UNIT
V/µs
ns
ns
Typical Performance Curves
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.5
0.45
450mW
0.4
0.35
0.3
0.25
0.2
θJA =22S0C°C70/W-6
0.15
0.1
0.05
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.55
0.5
500mW
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
VDD
SYNC CLAMP
VDD
VDD
+
-
CIN
IN
IN
RIN
75Ω
100nF
VDC
+
-
EN
GND
EN=GND: SHUTDOWN IDD~0
EN=VDD: ACTIVE IDD~2.0mA
SAG
NETWORK
OUT
R6
R7
SAG
R5
AC COUPLING
CAPACITOR
C5
47µF
C4
22µF
R4
75Ω
75Ω
FIGURE 3. BLOCK DIAGRAM
3
FN6142.1
August 15, 2005
Share Link: 