LC72720YVS-MPB-E 查看數據表（PDF） - ON Semiconductor

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LC72720YVS-MPB-E

RDS/RBDS Single-chip Signal Processor IC

ON Semiconductor 

LC72720YVS

(2) Synchronization detection method setting (1 bit) : BS

BS

Synchronization detection conditions

0

If during 3 blocks, 2 blocks of offset words were detected in the correct order.

1

If the offset words were detected in the correct order in 2 consecutive blocks.

Initial value : BS = 0

(3) Synchronization and RAM address reset (1 bit) : SYR

SYR

Synchronization detection circuit

0

Normal operation (reset cleared)

1

Forced to the unsynchronized state

(synchronization reset)

Initial value : SYR = 0

RAM

Normal write (See the description of the OWE bit)

After the reset is cleared, start writing from the data prior

to the establishment of synchronization, i.e. the data in

backward protection.

Caution : 1. To apply a synchronization reset, set SYR to 1 temporarily using CCB, and then set it back to 0 again using CCB.

The circuit will start synchronization capture operation at the point SYR is set to 0.

2. The SYR pin (pin30) also provides an identical reset control operation. Applications can use either method.

However, the control method that is not used must be set to 0 at all times.

Any pulse with a width of over 250 ns will suffice.

3. A reset must be applied immediately after the reception channel is changed.

If a reset is not applied, reception data from the previous channel may remain in on-chip memory.

4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding

the establishment of synchronization.

(4) RAM write control (1 bit) : OWE

OWE

0

1

RAM write conditions

Only data for which synchronization had been established is written.

Data for which synchronization not has been established (unsynchronized data) is also

written. (However, this applies when SYR = 0.)

Initial value : OWE = 0

(5) Error correction method setting (5 bits) : EC0 to EC4

EEE

CCC

012

000

100

010

110

001

101

011

111

Number of bits corrected

0 (error detection only)

1 or fewer bits

2 or fewer bits

3 or fewer bits

4 or fewer bits

5 or fewer bits

Illegal value

Illegal value

EE

CC

34

00

10

01

11

Initial values : EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1

Soft-decision setting

MODE0 Hard decision

MODE1 Soft decision A

MODE2 Soft decision B

Illegal value

Caution : 1. If soft-decision A or soft-decision B is specified, soft-decision control will be performed even if the number

of bits corrected is set to 0 (error detection only). With these settings, data will be output for blocks with no errors.

2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction.

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