LC72720YVS-TLM-E 查看數據表（PDF） - ON Semiconductor
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LC72720YVS-TLM-E Datasheet PDF : 19 Pages
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LC72720YVS
(6) Crystal oscillator frequency selection (1 bit) : XS
XS = 0 : 4.332 MHz (Initial value : XS = 0)
XS = 1 : 8.664 MHz
(7) Demodulation circuit phase control (2 bits) : PL0, PL1
PL0
PL1
Demodulation circuit phase control
0
0/1 Normal operation when ARI presence or absence is unclear.
0
If the circuit determines that the ARI signal is absent : 90 phase
1
1
If the circuit determines that the ARI signal is present : 0 phase
Initial values : PL0 = 0, PL1 = 1
Caution : 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces
the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier.
However, the initial phase following a synchronization reset is set by PL1.
2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90 (PL1 = 0) or
0 (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the
RDS data is reproduced by detecting at a phase of 90 with respect to the reproduced carrier. When ARI is present,
PL1 should be set to 1, since detection is at 0. In cases where the ARI presence is known in advance, more stable
reproduction can be achieved by fixing the demodulation phase in this manner.
(8) RDS/RBDS(MMBS) selection (1 bit) : RM
RM
RBDS
Decoding method
0
None Only RDS data is decoded correctly (Offset word E is not detected.)
1
Provided RDS and MMBS data is decoded correctly (Offset word E is also detected.)
Initial value : RM=0
(9) Output pin settings (3 bits) : PT0 to PT2
These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins
P P P T3
T4
T5
T6
T7
MODE T T T RDCL RDDA RSFT ERROR 57K BE1 CORREC ARI-ID BE0
012
0 0 0 0
1
1 0 0
2
0 1 0
3
1 1 0
4 0 0 1
5
1 0 1
6
0 1 1
7
1 1 1
: open, , : Output enabled ( = reverse polarity)
Initial value : PT0 = 1, PT1 = 1, PT2 = 0 (Mode 3)
Caution : 1. When PT2 is set to 1, the polarity of the T3(RDCL), T6(ERROR/57K), T7(CORREC/ARI-ID), SYNC,
and RDS-ID pins changes to active high.
2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors
to output data.
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