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TLP701A 查看數據表(PDF) - Toshiba

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TLP701A Datasheet PDF : 16 Pages
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TLP701A
11. Switching Characteristics (Note)
(Unless otherwise specified, Ta = -40 to 100 )
Characteristics
Symbol
Note
Test
Circuit
Test Condition
Min Typ. Max Unit
Propagation delay time
(L/H)
tpLH (Note 1) Fig. IF = 0 5 mA, VCC = 30 V,
12.1.7 Rg = 47 , Cg = 3 nF
30
500
ns
Propagation delay time
(H/L)
tpHL (Note 1)
IF = 5 0 mA, VCC = 30 V,
Rg = 47 , Cg = 3 nF
30
500
Rise time
Fall time
Pulse width distortion
Common-mode transient
immunity at output high
tr
(Note 1)
tf
(Note 1)
|tpHL-tpLH| (Note 1)
CMH (Note 2)
Fig.
12.1.8
IF = 0 5 mA, VCC = 30 V,
Rg = 47 , Cg = 3 nF
IF = 5 0 mA, VCC = 30 V,
Rg = 47 , Cg = 3 nF
IF = 0 ←→ 5 mA, VCC = 30 V,
Rg = 47 , Cg = 3 nF
VCM = 1000 Vp-p, IF = 5 mA,
VCC = 30 V, Ta = 25 ,
VO(min) = 26 V
50
50
350
±20 ±25
kV/µs
Common-mode transient
immunity at output low
CML (Note 3)
VCM = 1000 Vp-p, IF = 0 mA,
VCC = 30 V, Ta = 25 ,
VO(max) = 1 V
±20 ±25
Note: All typical values are at Ta = 25 .
Note 1: Input signal ( f = 25 kHz, duty = 50 %, tr = tf = 5 ns or less ).
CL is approximately 15 pF which includes probe and stray wiring capacitance.
Note 2: CMH is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic high state (VO > 26 V).
Note 3: CML is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in
the logic low state (VO < 1 V).
©2015 Toshiba Corporation
5
2015-12-25
Rev.5.0

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