LV4904VGEVB 查看數據表（PDF） - ON Semiconductor

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LV4904VGEVB

Digital Input Class-D Power Amplifier

ON Semiconductor 

5.4 Data read

LV4904V

By sending the data read command, the data held in the registers of the LV4904V can be read. To read the data, first the

address is sent using a dummy write cycle, and then operation is restarted. Next, after the device ID and read flag has

been sent in the read cycle, the LV4904V outputs the data of the address sent in the dummy write cycle to the SDA line.

The transmission side establishes the I2C bus-free state to prepare for data reception. After the data has been received,

ACK is not returned, and the stop condition is sent to end communication.

LV4904V

LV4904V

LV4904V

LV4904V

start Device ID R/W ACK

Read Address

Read Address

Dummy Write Cycle

ACK start Device ID R/W ACK

Read Address

Read Data

Read Cycle

stop

5.5 Internal register initialization

The internal registers accessed at address FFh through the I2C bus are write-only registers. By writing the value of FFh

into these registers, the internal registers are reset to the initial values.

LV4904V

LV4904V

LV4904V

start 1 1 0 1 1 0 0 R/W ACK 1 1 1 1 1 1 1 1 ACK 1 1 1 1 1 1 1 1 ACK stop

Write Address=0xFF

Write Data=0xFF

6. I2C Register Map

Register

STAT

DATA

GAINL

GAINR

MISC

RST

Address

00h

10h

20h

21h

30h

FFh

7. I2C Command List

D7

0

PSTPL

PSTPR

D6

D5

D4

D3

D2

D1

D0

MCKFS_I2C [1:0]

Last accessed address (read-only)

SRATE_I2C [1:0]

DFORM [2:0]

MUTEBL

GAINL [5:0]

MUTEBR

GAINR [5:0]

Reserved

NSORD

MDIDX

IDPEN

1

SOFTR [7: 0] (for initializing registers)

Register

Address

DATA

10h

GAINL

20h

GAINR

21h

MISC

30h

Bit

Signal Name

Pin Description

[2:0]

DFORM

3-wire serial PCM input, format setting

[4:3]

SRATE_I2C

3-wire serial PCM input, sampling rate setting

[6:5]

MCKFS_I2C

Master clock rate setting

[7]

0 (Fixed)

[5:0]

GAINL

Channel 1 (L channel), gain setting

[6]

MUTEBL

Channel 1 (L channel), mute setting

[7]

PSTPL

Channel 1 (L channel), output disable setting

[5:0]

GAINR

Channel 2 (R channel), gain setting

[6]

MUTEBR

Channel 2 (R channel), mute setting

[7]

PSTPR

Channel 2 (R channel), output disable setting

[0]

1 (Fixed)

[1]

IDPEN

Pulse operation control when muted

[2]

MDIDX

PWM modulation index setting

[3]

NSORD

Noise shaper order setting

Initial

Value

000

01

00

0

00000

0

0

00000

0

0

1

1

0

0

No.A1963-17/25

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