LV4904VGEVB 查看數據表（PDF） - ON Semiconductor

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LV4904VGEVB

Digital Input Class-D Power Amplifier

ON Semiconductor 

LV4904V

Left channel mute is set using MUTEBL and right channel mute is set using MUTEBR. Both MUTEBL and MUTEBR

are low active.

The settings established according to MUTEBL and MUTEBR are valid only when the MUTEB pin is low in the

combined I2C bus and pin setting mode. With any other pin settings or when the pin setting mode is established, the

settings established according to the pins described in section 2.10 are valid, therefore MUTEBL and MUTEBR setting

described here is ignored.

Table 8.2.2 shows the mute settings established according to MUTEBL and MUTEBR.

Table 8.2.2 Mute settings (initial value in bold)

MUTEBL/MUTEBR

0

1

Mute

Audio output ON

Setting

The left channel PWM output can be stopped by PSTPL and the right channel PWM output can be stopped by PSTPR.

Table 8.2.3 shows the PWM output stop settings established according to PSTPL and PSTPR.

Table 8.2.3 PWM output stop settings (initial value in bold)

PSTPL/PSTPR

0

1

8.3 Other settings

Setting

Normal output operation mode

PWM output stopped

Register

Address

D7

PWM1

41h

D6

D5

Reserved

D4

D3

D2

D1

D0

NSORD

MDIDX

IDPEN

1

By setting IDPEN, the PWM output can be fixed to the 50% duty cycle pulse or idled during mute or under no-signal

conditions.

Table 8.3.1 shows the IDPEN function settings.

Table 8.3.1 IDPEN function settings (initial value in bold).

IDPEN

0

1

Idle operation mode

50% duty pulse

Setting

The modulation index of the PWM modulator can be switched by setting MDIDX.

Table 8.3.2 shows the MDIDX function settings.

Table 8.3.2 MDIDX function settings (initial value in bold).

MDIDX

0

1

87.5%

100%

Setting

The noise shaper order can be switched by setting NSORD.

Table 8.3.3 shows the NSORD function settings.

Table 8.3.3 NSORD function settings (initial value in bold)

NSORD

0

1

Seventh order

Fifth order

Setting

No.A1963-20/25

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