LV4904V 查看數據表（PDF） - ON Semiconductor

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LV4904V

Digital Input Class-D Power Amplifier

ON Semiconductor 

2. Description of Pin Functions

LV4904V

2.1 Hardware reset pin (RSTB)

RSTB is a low active hardware reset pin.

The LV4904V is initialized by setting this pin to low. When the pin is set to low, the internal registers are cleared, and

the I2C bus registers are also reset to the initial values.

Table 2.1 shows the RSTB function settings.

Table 2.1 RSTB pin functions

RSTB

Setting

L

Hardware reset (registers cleared)

H

For normal operation

2.2 System enable pin (ENABLE)

ENABLE is the system enable pin of the LV4904V.

When this pin is set to low, the output is muted regardless of any other settings (mute, gain), and the PWM output is

stop(set to high-impedance). ENABLE must be set to high in order to activate the LV4904V.

If the ENABLE function does not need to be set to ON or OFF, the ENABLE pin can be fixed at high.

Table 2.2 shows the ENABLE function settings.

Table 2.2 ENABLE pin function settings

ENABLE

Setting

L

System disabled

H

System enabled

2.3 Master clock input pin (MCK)

The master clock is input from the MCK pin.

For details on this pin, refer to “8.1 Input data settings.”

2.4 3-wire serial data input pins (BCK, LRCK, SDIN)

BCK, LRCK and SDIN are pins used for 3-wire serial data input.

For details on these pins, refer to “8.1 Input data settings.”

2.5 I2C bus pins (SCL, SDA)

SCL and SDA are the pins used for I2C bus communication.

The I2C bus interface of the LV4904V does not function as the master but operates only as a slave.

SCL is the I2C bus clock pin and operates only as an input pin. This means that the LV4904V never requests wait by

pulling the SCL line to low. SDA is the I2C bus data pin, and since it is an N-channel open drain pin, the data line must

be pulled up.

For details on the I2C bus interface, refer to “5 I2C Bus Specifications.”

No.A1963-9/25

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