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LV4924VH 查看數據表(PDF) - ON Semiconductor

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LV4924VH Datasheet PDF : 16 Pages
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Reference data for thermal design
Overall view of substrate
LV4924VH
Mounted on a specified board (Customer bread board rev.1.0): 90.0mm × 70.0 mm × 1.6 mm (two-layer) Material: glass epoxy
Pd max-Ta
Pd max -- Ta
6
Specified board : 90.0 × 70.0 × 1.6mm3
5
Exposed Die-Pad
Soldered
glass epoxy
4.6
4
Exposed Die-Pad
Not Soldered
3.2
3
2.7
2
1.9
1
0
--25
0
25
50
75
100
Ambient temperature, Ta -- C
1. Data of the Exposed Die-Pad (heat spreader) substrate as mounted represents the value in the state where the exposed
Die-Pad surface is wet for 90% or more.
2. For the set design, derating design should be made while ensuring allowance.
Stresses to become an object of derating are the voltage, current, junction temperature, power loss and mechanical
stresses including vibration, impact and tension.
Accordingly, these stresses must be as low or small as possible in the design.
Approximate targets for general derating are as follows:
(1) Maximum value 80% or less for the voltage rating.
(2) Maximum value 80% or less for the current rating.
(3) Maximum value 80% or less for the temperature rating.
3. After set design, be sure to verify the design with the product.
Also check the soldered state of the Exposed Die-Pad, etc. and verify the reliability of the soldered joint.
If any void or deterioration is observed in these sections, thermal conduction to the substrate is deteriorated, resulting in
thermal damage of IC.
No.A1997-4/15

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