MT90820APR 查看數據表（PDF） - Zarlink Semiconductor Inc

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MT90820APR

Large Digital Switch

Zarlink Semiconductor Inc 

MT90820

Data Sheet

Pin Description

Pin #

84

100

PLCC MQFP

1, 11, 31, 41,

30, 54 56, 66,

64, 75 76, 99

2, 32, 5, 40,

63

67

3 - 10 68-75

Name

VSS

Ground.

Description

VDD +5 Volt Power Supply.

STo8 - 15 ST-BUS Output 8 to 15 (Three-state Outputs): Serial data Output stream. These

streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value

programmed at bits DR0 - 1 in the IMS register.

12 - 27 81-96

STi0 - 15 ST-BUS Input 0 to 15 (Inputs): Serial data input stream. These streams may have data

rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 -

1 in the IMS register.

28

97

F0i Frame Pulse (Input): When the WFPS pin is low, this input accepts and automatically

identifies frame synchronization signals formatted according to ST-BUS and GCI

specifications. When the WFPS pin is high, this pin accepts a negative frame pulse which

conforms to WFPS formats.

29

98 FE/HCLK Frame Evaluation / HCLK Clock (Input): When the WFPS pin is low, this pin is the

frame measurement input. When the WFPS pin is high, the HCLK (4.096 MHz clock) is

required for frame alignment in the wide frame pulse (WFP) mode.

31

100

CLK

Clock (Input): Serial clock for shifting data in/out on the serial streams (STi/o 0 - 15).

Depending upon the value programmed at bits DR0 - 1 in the IMS register, this input

accepts a 4.096, 8.192 or 16.384 MHz clock.

33

6

TMS

Test Mode Select (Input): JTAG signal that controls the state transitions of the TAP

controller. This pin is pulled high by an internal pull-up when not driven.

34

7

TDI Test Serial Data In (Input): JTAG serial test instructions and data are shifted in on this

pin. This pin is pulled high by an internal pull-up when not driven.

35

8

TDO

Test Serial Data Out (Output): JTAG serial data is output on this pin on the falling edge

of TCK. This pin is held in high impedance state when JTAG scan is not enable.

36

9

TCK

Test Clock (Input): Provides the clock to the JTAG test logic. This pin is pulled high by

an internal pull-up when not driven.

37

10

TRST

Test Reset (Input): Asynchronously initializes the JTAG TAP controller by putting it in

the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This

pin should be pulsed low on power-up, or held low, to ensure that the MT90820 is in the

normal functional mode.

38

11

IC

Internal Connection (Input): Connect to VSS for normal operation. This pin must be

low for the MT90820 to function normally and to comply with IEEE 1149 (JTAG)

boundary scan requirements. This pin is pulled low internally when not driven.

4

Zarlink Semiconductor Inc.

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