LF3320QC12 查看數據表（PDF） - LOGIC Devices
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LF3320QC12 Datasheet PDF : 24 Pages
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DEVICES INCORPORATED
LF3320
Horizontal Digital Image Filter
of loading data into Filter B limit
register 7. Data value 3B60H is loaded
as the lower limit and 72A4H is loaded
as the upper limit.
It takes 9S clock cycles to load S
coefficient sets into the device. There-
fore, it takes 2304 clock cycles to load
all 256 coefficient sets. Assuming an
83 MHz clock rate, all 256 coefficient
sets can be updated in less than 27.7 µs,
which is well within vertical blanking
time. It takes 5S clock cycles to load S
round or limit registers. Therefore, it
takes 320 clock cycles to update all
round and limit registers (both Filters A
and B). Assuming an 83 MHz clock
rate, all Filter A and B round/limit
registers can be updated in 3.84 µs.
FIGURE 17. COEFFICIENT BANK LOADING SEQUENCE
COEFFICIENT SET 1
COEFFICIENT SET 2
The coefficient banks and
Configuration/Control registers are not
loaded with data until all data values
for the specified address are loaded into
the LF InterfaceTM. In other words, the
coefficient banks are not written to until
all eight coefficients have been loaded
into the LF InterfaceTM. A round register is
not written to until all four data values
are loaded.
COEFFICIENT SET 3
CLK
LDA/LDB
CFA/CFB11-0
ADDR1 COEF0
W1
COEF7 ADDR2 COEF0
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
W2
COEF7 ADDR3 COEF0
W3
COEF7
FIGURE 18. CONFIGURATION/CONTROL REGISTER LOADING SEQUENCE
CONFIG REG SELECT REG
ROUND REGISTER
LIMIT REGISTER
CLK
LDA/LDB
CFA/CFB11-0
W1
W2
W3
W4
ADDR1 DATA1 ADDR2 DATA1 ADDR3 DATA1 DATA2 DATA3 DATA4 ADDR4 DATA1 DATA2 DATA3 DATA4
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
FIGURE 19. COEFFICIENT BANK LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
COEFFICIENT SET 1
CLK
PAUSEA/PAUSEB
LDA/LDB
CFA/CFB11-0
ADDR1
COEF0
COEF1
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W1
COEF7
Video Imaging Products
2-16
08/16/2000–LDS.3320-N
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